154 lines
5.3 KiB
C
154 lines
5.3 KiB
C
/*
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* Copyright 2022 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _shader_code_h_
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#define _shader_code_h_
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#ifndef ARRAY_SIZE
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#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
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#endif
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enum amdgpu_test_gfx_version {
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AMDGPU_TEST_GFX_V9 = 0,
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AMDGPU_TEST_GFX_V10,
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AMDGPU_TEST_GFX_V11,
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AMDGPU_TEST_GFX_MAX,
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};
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enum cs_type {
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CS_BUFFERCLEAR = 0,
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CS_BUFFERCOPY,
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CS_HANG,
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CS_HANG_SLOW,
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};
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enum ps_type {
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PS_CONST,
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PS_TEX,
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PS_HANG,
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PS_HANG_SLOW
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};
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enum vs_type {
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VS_RECTPOSTEXFAST,
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};
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struct reg_info {
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uint32_t reg_offset; ///< Memory mapped register offset
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uint32_t reg_value; ///< register value
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};
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#include "shader_code_hang.h"
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#include "shader_code_gfx9.h"
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#include "shader_code_gfx10.h"
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#include "shader_code_gfx11.h"
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struct shader_test_cs_shader {
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const uint32_t *shader;
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uint32_t shader_size;
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const struct reg_info *sh_reg;
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uint32_t num_sh_reg;
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const struct reg_info *context_reg;
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uint32_t num_context_reg;
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};
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struct shader_test_ps_shader {
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const uint32_t *shader;
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unsigned shader_size;
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const uint32_t patchinfo_code_size;
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const uint32_t *patchinfo_code;
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const uint32_t *patchinfo_code_offset;
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const struct reg_info *sh_reg;
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const uint32_t num_sh_reg;
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const struct reg_info *context_reg;
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const uint32_t num_context_reg;
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};
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struct shader_test_vs_shader {
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const uint32_t *shader;
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uint32_t shader_size;
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const struct reg_info *sh_reg;
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uint32_t num_sh_reg;
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const struct reg_info *context_reg;
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uint32_t num_context_reg;
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};
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static const struct shader_test_cs_shader shader_test_cs[AMDGPU_TEST_GFX_MAX][2] = {
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// gfx9, cs_bufferclear
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{{bufferclear_cs_shader_gfx9, sizeof(bufferclear_cs_shader_gfx9), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)},
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// gfx9, cs_buffercopy
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{buffercopy_cs_shader_gfx9, sizeof(buffercopy_cs_shader_gfx9), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}},
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// gfx10, cs_bufferclear
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{{bufferclear_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)},
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// gfx10, cs_buffercopy
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{buffercopy_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}},
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// gfx11, cs_bufferclear
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{{bufferclear_cs_shader_gfx11, sizeof(bufferclear_cs_shader_gfx11), bufferclear_cs_shader_registers_gfx11, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx11)},
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// gfx11, cs_buffercopy
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{buffercopy_cs_shader_gfx11, sizeof(bufferclear_cs_shader_gfx11), bufferclear_cs_shader_registers_gfx11, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx11)}},
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};
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#define SHADER_PS_INFO(_ps, _n) \
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{ps_##_ps##_shader_gfx##_n, sizeof(ps_##_ps##_shader_gfx##_n), \
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ps_##_ps##_shader_patchinfo_code_size_gfx##_n, \
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ps_##_ps##_shader_patchinfo_code_gfx##_n, \
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ps_##_ps##_shader_patchinfo_offset_gfx##_n, \
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ps_##_ps##_sh_registers_gfx##_n, ps_##_ps##_num_sh_registers_gfx##_n, \
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ps_##_ps##_context_registers_gfx##_n, ps_##_ps##_num_context_registers_gfx##_n}
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static const struct shader_test_ps_shader shader_test_ps[AMDGPU_TEST_GFX_MAX][2] = {
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{SHADER_PS_INFO(const, 9), SHADER_PS_INFO(tex, 9)},
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{SHADER_PS_INFO(const, 10), SHADER_PS_INFO(tex, 10)},
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{SHADER_PS_INFO(const, 11), SHADER_PS_INFO(tex, 11)},
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};
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#define SHADER_VS_INFO(_vs, _n) \
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{vs_##_vs##_shader_gfx##_n, sizeof(vs_##_vs##_shader_gfx##_n), \
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vs_##_vs##_sh_registers_gfx##_n, vs_##_vs##_num_sh_registers_gfx##_n, \
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vs_##_vs##_context_registers_gfx##_n, vs_##_vs##_num_context_registers_gfx##_n}
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static const struct shader_test_vs_shader shader_test_vs[AMDGPU_TEST_GFX_MAX][1] = {
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{SHADER_VS_INFO(RectPosTexFast, 9)},
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{SHADER_VS_INFO(RectPosTexFast, 10)},
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{SHADER_VS_INFO(RectPosTexFast, 11)},
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};
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struct shader_test_gfx_info {
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const uint32_t *preamble_cache;
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uint32_t size_preamble_cache;
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const uint32_t *cached_cmd;
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uint32_t size_cached_cmd;
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uint32_t sh_reg_base;
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uint32_t context_reg_base;
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};
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#define SHADER_TEST_GFX_INFO(_n) \
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preamblecache_gfx##_n, sizeof(preamblecache_gfx##_n), \
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cached_cmd_gfx##_n, sizeof(cached_cmd_gfx##_n), \
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sh_reg_base_gfx##_n, context_reg_base_gfx##_n
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static struct shader_test_gfx_info shader_test_gfx_info[AMDGPU_TEST_GFX_MAX] = {
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{SHADER_TEST_GFX_INFO(9),},
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{SHADER_TEST_GFX_INFO(10),},
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{SHADER_TEST_GFX_INFO(11),},
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};
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#endif
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