395 lines
11 KiB
C
395 lines
11 KiB
C
/*
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* Copyright 2008 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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*/
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#include "drmP.h"
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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#include "r300_reg.h"
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int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
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{
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struct drm_radeon_private *dev_priv = dev->dev_private;
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struct drm_radeon_cs *cs = data;
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uint32_t *packets = NULL;
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uint32_t cs_id;
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uint32_t card_offset;
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void *ib = NULL;
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long size;
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int r;
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RING_LOCALS;
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/* set command stream id to 0 which is fake id */
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cs_id = 0;
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DRM_COPY_TO_USER(&cs->cs_id, &cs_id, sizeof(uint32_t));
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if (dev_priv == NULL) {
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DRM_ERROR("called with no initialization\n");
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return -EINVAL;
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}
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if (!cs->dwords) {
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return 0;
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}
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/* limit cs to 64K ib */
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if (cs->dwords > (16 * 1024)) {
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return -EINVAL;
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}
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/* copy cs from userspace maybe we should copy into ib to save
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* one copy but ib will be mapped wc so not good for cmd checking
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* somethings worth testing i guess (Jerome)
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*/
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size = cs->dwords * sizeof(uint32_t);
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packets = drm_alloc(size, DRM_MEM_DRIVER);
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if (packets == NULL) {
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return -ENOMEM;
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}
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if (DRM_COPY_FROM_USER(packets, (void __user *)(unsigned long)cs->packets, size)) {
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r = -EFAULT;
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goto out;
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}
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/* get ib */
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r = dev_priv->cs.ib_get(dev, &ib, cs->dwords, &card_offset);
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if (r) {
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goto out;
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}
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/* now parse command stream */
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r = dev_priv->cs.parse(dev, fpriv, ib, packets, cs->dwords);
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if (r) {
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goto out;
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}
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BEGIN_RING(4);
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OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
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OUT_RING(card_offset);
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OUT_RING(cs->dwords);
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OUT_RING(CP_PACKET2());
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ADVANCE_RING();
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/* emit cs id sequence */
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dev_priv->cs.id_emit(dev, &cs_id);
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COMMIT_RING();
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DRM_COPY_TO_USER(&cs->cs_id, &cs_id, sizeof(uint32_t));
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out:
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dev_priv->cs.ib_free(dev, ib, cs->dwords);
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drm_free(packets, size, DRM_MEM_DRIVER);
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return r;
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}
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/* for non-mm */
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static int radeon_nomm_relocate(struct drm_device *dev, struct drm_file *file_priv, uint32_t *reloc, uint32_t *offset)
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{
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*offset = reloc[1];
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return 0;
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}
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#define RELOC_SIZE 2
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#define RADEON_2D_OFFSET_MASK 0x3fffff
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static __inline__ int radeon_cs_relocate_packet0(struct drm_device *dev, struct drm_file *file_priv,
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uint32_t *packets, uint32_t offset_dw)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t hdr = packets[offset_dw];
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uint32_t reg = (hdr & R300_CP_PACKET0_REG_MASK) << 2;
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uint32_t val = packets[offset_dw + 1];
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uint32_t packet3_hdr = packets[offset_dw+2];
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uint32_t tmp, offset;
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int ret;
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/* this is too strict we may want to expand the length in the future and have
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old kernels ignore it. */
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if (packet3_hdr != (RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16))) {
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DRM_ERROR("Packet 3 was %x should have been %x: reg is %x\n", packet3_hdr, RADEON_CP_PACKET3 | RADEON_CP_NOP | (RELOC_SIZE << 16), reg);
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return -EINVAL;
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}
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switch(reg) {
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case RADEON_DST_PITCH_OFFSET:
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case RADEON_SRC_PITCH_OFFSET:
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/* pass in the start of the reloc */
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ret = dev_priv->cs.relocate(dev, file_priv, packets + offset_dw + 2, &offset);
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if (ret)
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return ret;
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tmp = (val & RADEON_2D_OFFSET_MASK) << 10;
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val &= ~RADEON_2D_OFFSET_MASK;
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offset += tmp;
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offset >>= 10;
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val |= offset;
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break;
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case RADEON_RB3D_COLOROFFSET:
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case R300_RB3D_COLOROFFSET0:
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case R300_ZB_DEPTHOFFSET:
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case R300_TX_OFFSET_0:
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case R300_TX_OFFSET_0+4:
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case R200_PP_TXOFFSET_0:
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case R200_PP_TXOFFSET_1:
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case RADEON_PP_TXOFFSET_0:
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case RADEON_PP_TXOFFSET_1:
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ret = dev_priv->cs.relocate(dev, file_priv, packets + offset_dw + 2, &offset);
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if (ret)
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return ret;
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offset &= 0xffffffe0;
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val += offset;
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break;
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default:
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break;
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}
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packets[offset_dw + 1] = val;
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return 0;
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}
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static int radeon_cs_relocate_packet3(struct drm_device *dev, struct drm_file *file_priv,
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uint32_t *packets, uint32_t offset_dw)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t hdr = packets[offset_dw];
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int num_dw = (hdr & RADEON_CP_PACKET_COUNT_MASK) >> 16;
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uint32_t reg = hdr & 0xff00;
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uint32_t offset, val, tmp;
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int ret;
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switch(reg) {
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case RADEON_CNTL_HOSTDATA_BLT:
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{
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val = packets[offset_dw + 2];
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ret = dev_priv->cs.relocate(dev, file_priv, packets + offset_dw + num_dw + 2, &offset);
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if (ret)
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return ret;
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tmp = (val & RADEON_2D_OFFSET_MASK) << 10;
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val &= ~RADEON_2D_OFFSET_MASK;
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offset += tmp;
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offset >>= 10;
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val |= offset;
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packets[offset_dw + 2] = val;
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}
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default:
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return -EINVAL;
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}
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return 0;
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}
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int radeon_cs_packet0(struct drm_device *dev, struct drm_file *file_priv,
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uint32_t *packets, uint32_t offset_dw)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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uint32_t hdr = packets[offset_dw];
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int num_dw = ((hdr & RADEON_CP_PACKET_COUNT_MASK) >> 16) + 2;
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int need_reloc = 0;
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int reg = (hdr & R300_CP_PACKET0_REG_MASK) << 2;
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int count_dw = 1;
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int ret;
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while (count_dw < num_dw) {
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/* need to have something like the r300 validation here -
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list of allowed registers */
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int flags;
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ret = r300_check_range(reg, 1);
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switch(ret) {
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case -1:
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DRM_ERROR("Illegal register %x\n", reg);
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break;
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case 0:
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break;
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case 1:
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flags = r300_get_reg_flags(reg);
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if (flags == MARK_CHECK_OFFSET) {
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if (num_dw > 2) {
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DRM_ERROR("Cannot relocate inside type stream of reg0 packets\n");
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return -EINVAL;
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}
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ret = radeon_cs_relocate_packet0(dev, file_priv, packets, offset_dw);
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if (ret)
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return ret;
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DRM_DEBUG("need to relocate %x %d\n", reg, flags);
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/* okay it should be followed by a NOP */
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} else if (flags == MARK_CHECK_SCISSOR) {
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DRM_DEBUG("need to validate scissor %x %d\n", reg, flags);
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} else {
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DRM_DEBUG("illegal register %x %d\n", reg, flags);
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return -EINVAL;
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}
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break;
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}
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count_dw++;
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reg += 4;
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}
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return 0;
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}
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int radeon_cs_parse(struct drm_device *dev, struct drm_file *file_priv,
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void *ib, uint32_t *packets, uint32_t dwords)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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volatile int rb;
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int size_dw = dwords;
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/* scan the packet for various things */
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int count_dw = 0;
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int ret = 0;
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while (count_dw < size_dw && ret == 0) {
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int hdr = packets[count_dw];
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int num_dw = (hdr & RADEON_CP_PACKET_COUNT_MASK) >> 16;
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int reg;
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switch (hdr & RADEON_CP_PACKET_MASK) {
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case RADEON_CP_PACKET0:
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ret = radeon_cs_packet0(dev, file_priv, packets, count_dw);
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break;
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case RADEON_CP_PACKET1:
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case RADEON_CP_PACKET2:
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reg = hdr & RADEON_CP_PACKET0_REG_MASK;
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DRM_DEBUG("Packet 1/2: %d %x\n", num_dw, reg);
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break;
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case RADEON_CP_PACKET3:
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reg = hdr & 0xff00;
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switch(reg) {
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case RADEON_CNTL_HOSTDATA_BLT:
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radeon_cs_relocate_packet3(dev, file_priv, packets, count_dw);
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break;
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case RADEON_CNTL_BITBLT_MULTI:
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case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */
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case RADEON_CP_INDX_BUFFER:
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DRM_ERROR("need relocate packet 3 for %x\n", reg);
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break;
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case RADEON_3D_DRAW_IMMD: /* triggers drawing using in-packet vertex data */
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case RADEON_CP_3D_DRAW_IMMD_2: /* triggers drawing using in-packet vertex data */
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case RADEON_CP_3D_DRAW_VBUF_2: /* triggers drawing of vertex buffers setup elsewhere */
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case RADEON_CP_3D_DRAW_INDX_2: /* triggers drawing using indices to vertex buffer */
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case RADEON_WAIT_FOR_IDLE:
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case RADEON_CP_NOP:
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break;
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default:
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DRM_ERROR("unknown packet 3 %x\n", reg);
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ret = -EINVAL;
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}
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break;
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}
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count_dw += num_dw+2;
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}
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if (ret)
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return ret;
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/* copy the packet into the IB */
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memcpy(ib, packets, dwords * sizeof(uint32_t));
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/* read back last byte to flush WC buffers */
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rb = readl((ib + (dwords-1) * sizeof(uint32_t)));
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return 0;
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}
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uint32_t radeon_cs_id_get(struct drm_radeon_private *radeon)
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{
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/* FIXME: protect with a spinlock */
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/* FIXME: check if wrap affect last reported wrap & sequence */
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radeon->cs.id_scnt = (radeon->cs.id_scnt + 1) & 0x00FFFFFF;
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if (!radeon->cs.id_scnt) {
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/* increment wrap counter */
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radeon->cs.id_wcnt += 0x01000000;
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/* valid sequence counter start at 1 */
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radeon->cs.id_scnt = 1;
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}
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return (radeon->cs.id_scnt | radeon->cs.id_wcnt);
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}
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void r100_cs_id_emit(struct drm_device *dev, uint32_t *id)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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RING_LOCALS;
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/* ISYNC_CNTL should have CPSCRACTH bit set */
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*id = radeon_cs_id_get(dev_priv);
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/* emit id in SCRATCH4 (not used yet in old drm) */
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BEGIN_RING(2);
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OUT_RING(CP_PACKET0(RADEON_SCRATCH_REG4, 0));
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OUT_RING(*id);
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ADVANCE_RING();
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}
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void r300_cs_id_emit(struct drm_device *dev, uint32_t *id)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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RING_LOCALS;
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/* ISYNC_CNTL should not have CPSCRACTH bit set */
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*id = radeon_cs_id_get(dev_priv);
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/* emit id in SCRATCH6 */
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BEGIN_RING(8);
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OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 0));
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OUT_RING(6);
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OUT_RING(CP_PACKET0(R300_CP_RESYNC_DATA, 0));
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OUT_RING(*id);
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OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
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OUT_RING(R300_RB3D_DC_FINISH);
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RADEON_WAIT_UNTIL_3D_IDLE();
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ADVANCE_RING();
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}
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uint32_t r100_cs_id_last_get(struct drm_device *dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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return GET_SCRATCH(4);
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}
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uint32_t r300_cs_id_last_get(struct drm_device *dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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return GET_SCRATCH(6);
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}
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int radeon_cs_init(struct drm_device *dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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if (dev_priv->chip_family < CHIP_RV280) {
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dev_priv->cs.id_emit = r100_cs_id_emit;
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dev_priv->cs.id_last_get = r100_cs_id_last_get;
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} else if (dev_priv->chip_family < CHIP_R600) {
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dev_priv->cs.id_emit = r300_cs_id_emit;
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dev_priv->cs.id_last_get = r300_cs_id_last_get;
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}
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dev_priv->cs.parse = radeon_cs_parse;
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/* ib get depends on memory manager or not so memory manager */
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dev_priv->cs.relocate = radeon_nomm_relocate;
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return 0;
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}
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