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drm/shared-core/nouveau_drv.h

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initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
/*
* Copyright 2005 Stephane Marchesin.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __NOUVEAU_DRV_H__
#define __NOUVEAU_DRV_H__
#define DRIVER_AUTHOR "Stephane Marchesin"
#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
#define DRIVER_NAME "nouveau"
#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
#define DRIVER_DATE "20060213"
Merge the pciid work. Add getparams for AGP and FB physical adresses. Fix the MEM_ALLOC issue properly. Fix context switches for nv44. Change the DRM version to 0.0.1.
2006-12-03 02:02:54 -07:00
#define DRIVER_MAJOR 0
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
#define DRIVER_MINOR 0
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
#define DRIVER_PATCHLEVEL 6
initial import of nouveau code from nouveau CVS
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#define NOUVEAU_FAMILY 0x0000FFFF
#define NOUVEAU_FLAGS 0xFFFF0000
#include "nouveau_drm.h"
#include "nouveau_reg.h"
nouveau: Add nv40-specific PGRAPH code, not hooked up yet.
2007-01-01 20:52:43 -07:00
struct mem_block {
struct mem_block *next;
struct mem_block *prev;
uint64_t start;
uint64_t size;
DRMFILE filp; /* 0: free, -1: heap, other: real files */
int flags;
drm_local_map_t *map;
};
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
enum nouveau_flags {
NV_NFORCE =0x10000000,
NV_NFORCE2 =0x20000000
};
struct nouveau_object
{
struct nouveau_object *next;
struct nouveau_object *prev;
nouveau: associate all created objects with a channel + cleanups
2007-03-12 21:18:03 -06:00
int channel;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
Use nouveau_mem.c to allocate RAMIN.
2006-11-29 16:31:42 -07:00
struct mem_block *instance;
uint32_t ht_loc;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
uint32_t handle;
int class;
int engine;
};
struct nouveau_fifo
{
int used;
/* owner of this fifo */
DRMFILE filp;
/* mapping of the fifo itself */
drm_local_map_t *map;
/* mapping of the regs controling the fifo */
drm_local_map_t *regs;
Restructure initialisation a bit. - Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-13 14:11:49 -07:00
/* dma object for the command buffer itself */
nouveau: Alloc cmdbuf for each channel individually
2006-12-26 05:30:26 -07:00
struct mem_block *cmdbuf_mem;
Restructure initialisation a bit. - Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-13 14:11:49 -07:00
struct nouveau_object *cmdbuf_obj;
nouveau: Add nv40-specific PGRAPH code, not hooked up yet.
2007-01-01 20:52:43 -07:00
/* PGRAPH context, for cards that keep it in RAMIN */
struct mem_block *ramin_grctx;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
/* objects belonging to this fifo */
struct nouveau_object *objs;
Add basic pgraph context for nv10. It only fake a context switch : pgraph state are not save/restored.
2007-01-05 11:40:11 -07:00
nouveau: first step to make graph ctx works It is still not working, but now we could use some 3D commands without needed to run nvidia blob before.
2007-01-13 13:43:47 -07:00
/* XXX dynamic alloc ? */
nouveau: fix nv04 graph routines for new register names.
2007-02-02 21:25:36 -07:00
uint32_t pgraph_ctx [340];
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
};
Allow cmdbuf location(AGP,VRAM) and size to be configured.
2006-09-02 14:36:06 -06:00
struct nouveau_config {
struct {
int location;
int size;
} cmdbuf;
};
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
struct nouveau_engine_func {
struct {
nouveau: rename engtab functions
2007-06-24 02:54:36 -06:00
int (*init)(drm_device_t *dev);
void (*takedown)(drm_device_t *dev);
} mc;
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
struct {
nouveau: rename engtab functions
2007-06-24 02:54:36 -06:00
int (*init)(drm_device_t *dev);
void (*takedown)(drm_device_t *dev);
} timer;
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
struct {
nouveau: rename engtab functions
2007-06-24 02:54:36 -06:00
int (*init)(drm_device_t *dev);
void (*takedown)(drm_device_t *dev);
} fb;
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
struct {
nouveau: prototype PFIFO/PGRAPH engtab API
2007-06-24 02:54:51 -06:00
int (*init)(drm_device_t *);
void (*takedown)(drm_device_t *);
int (*create_context)(drm_device_t *, int channel);
void (*destroy_context)(drm_device_t *, int channel);
int (*load_context)(drm_device_t *, int channel);
int (*save_context)(drm_device_t *, int channel);
nouveau: rename engtab functions
2007-06-24 02:54:36 -06:00
} graph;
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
struct {
nouveau: prototype PFIFO/PGRAPH engtab API
2007-06-24 02:54:51 -06:00
int (*init)(drm_device_t *);
void (*takedown)(drm_device_t *);
int (*create_context)(drm_device_t *, int channel);
void (*destroy_context)(drm_device_t *, int channel);
int (*load_context)(drm_device_t *, int channel);
int (*save_context)(drm_device_t *, int channel);
nouveau: rename engtab functions
2007-06-24 02:54:36 -06:00
} fifo;
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
};
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
typedef struct drm_nouveau_private {
/* the card type, takes NV_* as values */
int card_type;
nouveau: determine chipset type at startup, instead of every time we use it.
2007-01-28 05:48:33 -07:00
/* exact chipset, derived from NV_PMC_BOOT_0 */
int chipset;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
int flags;
drm_local_map_t *mmio;
drm_local_map_t *fb;
nouveau: map pci resource 2 on >=nv40
2007-01-07 05:56:45 -07:00
drm_local_map_t *ramin; /* NV40 onwards */
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
Hack around yet another "X restart borkage without nouveau.ko reload" problem. On X init, PFIFO and PGRAPH are reset to defaults. This causes the GPU to loose the configuration done by the drm. Perhaps a CARD_INIT ioctl a proper solution to having this problem again in the future..
2006-11-13 10:51:13 -07:00
int fifo_alloc_count;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
struct nouveau_fifo fifos[NV_MAX_FIFO_NUMBER];
Use nouveau_mem.c to allocate RAMIN.
2006-11-29 16:31:42 -07:00
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
struct nouveau_engine_func Engine;
nouveau: avoid allocating vram that's used as instance memory.
2007-01-07 06:37:39 -07:00
/* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
uint32_t ramin_size;
Restructure initialisation a bit. - Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-13 14:11:49 -07:00
uint32_t ramht_offset;
uint32_t ramht_size;
uint32_t ramht_bits;
Context switching work. Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet). Removed the PFIFO_REINIT ioctl. I hope it's that a good idea... Requires the upcoming commit to the DDX.
2006-10-10 16:28:15 -06:00
uint32_t ramfc_offset;
Restructure initialisation a bit. - Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-13 14:11:49 -07:00
uint32_t ramfc_size;
Context switching work. Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet). Removed the PFIFO_REINIT ioctl. I hope it's that a good idea... Requires the upcoming commit to the DDX.
2006-10-10 16:28:15 -06:00
uint32_t ramro_offset;
Restructure initialisation a bit. - Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-13 14:11:49 -07:00
uint32_t ramro_size;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
Merge the pciid work. Add getparams for AGP and FB physical adresses. Fix the MEM_ALLOC issue properly. Fix context switches for nv44. Change the DRM version to 0.0.1.
2006-12-03 02:02:54 -07:00
/* base physical adresses */
uint64_t fb_phys;
nouveau: intrusive drm interface changes graphics objects: - No longer takes flags/dmaobj parameters, requires some major changes to the ddx to setup the object through the FIFO. This change is likely to cause breakages on some cards (tested on NV05,NV28,NV35, NV40 and NV4E). dma objects: - now takes a "class" parameter, not really used yet but we may need it at some point. - parameters are checked, so clients can't randomly create DMA objects pointing at whatever they feel like. misc: - Added FB_SIZE/AGP_SIZE getparams - Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR - Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't NOTIFICATION_PENDING.
2007-02-27 21:14:08 -07:00
uint64_t fb_available_size;
Merge the pciid work. Add getparams for AGP and FB physical adresses. Fix the MEM_ALLOC issue properly. Fix context switches for nv44. Change the DRM version to 0.0.1.
2006-12-03 02:02:54 -07:00
uint64_t agp_phys;
nouveau: intrusive drm interface changes graphics objects: - No longer takes flags/dmaobj parameters, requires some major changes to the ddx to setup the object through the FIFO. This change is likely to cause breakages on some cards (tested on NV05,NV28,NV35, NV40 and NV4E). dma objects: - now takes a "class" parameter, not really used yet but we may need it at some point. - parameters are checked, so clients can't randomly create DMA objects pointing at whatever they feel like. misc: - Added FB_SIZE/AGP_SIZE getparams - Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR - Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't NOTIFICATION_PENDING.
2007-02-27 21:14:08 -07:00
uint64_t agp_available_size;
Merge the pciid work. Add getparams for AGP and FB physical adresses. Fix the MEM_ALLOC issue properly. Fix context switches for nv44. Change the DRM version to 0.0.1.
2006-12-03 02:02:54 -07:00
nouveau: Add an mtrr over the whole FB
2007-01-05 12:49:34 -07:00
/* the mtrr covering the FB */
int fb_mtrr;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
struct mem_block *agp_heap;
struct mem_block *fb_heap;
struct mem_block *fb_nomap_heap;
Use nouveau_mem.c to allocate RAMIN.
2006-11-29 16:31:42 -07:00
struct mem_block *ramin_heap;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
nouveau: get nv30 context switching to work. * Pulled in some registers from nv10reg.h. Needed for context switching. * Filled in nv30 graphics context (based on nv40_graph.c). * Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-11 22:13:05 -07:00
/* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
uint32_t ctx_table_size;
struct mem_block *ctx_table;
Allow cmdbuf location(AGP,VRAM) and size to be configured.
2006-09-02 14:36:06 -06:00
struct nouveau_config config;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
}
drm_nouveau_private_t;
/* nouveau_state.c */
extern void nouveau_preclose(drm_device_t * dev, DRMFILE filp);
extern int nouveau_load(struct drm_device *dev, unsigned long flags);
extern int nouveau_firstopen(struct drm_device *dev);
nouveau: Add an mtrr over the whole FB
2007-01-05 12:49:34 -07:00
extern void nouveau_lastclose(struct drm_device *dev);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
extern int nouveau_unload(struct drm_device *dev);
Add stub {get,set}param ioctls.
2006-08-30 00:55:02 -06:00
extern int nouveau_ioctl_getparam(DRM_IOCTL_ARGS);
extern int nouveau_ioctl_setparam(DRM_IOCTL_ARGS);
Context switching work. Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet). Removed the PFIFO_REINIT ioctl. I hope it's that a good idea... Requires the upcoming commit to the DDX.
2006-10-10 16:28:15 -06:00
extern void nouveau_wait_for_idle(struct drm_device *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
extern int nouveau_ioctl_card_init(DRM_IOCTL_ARGS);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
/* nouveau_mem.c */
extern uint64_t nouveau_mem_fb_amount(struct drm_device *dev);
extern void nouveau_mem_release(DRMFILE filp, struct mem_block *heap);
extern int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS);
extern int nouveau_ioctl_mem_free(DRM_IOCTL_ARGS);
extern struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, uint64_t size, int flags, DRMFILE filp);
extern void nouveau_mem_free(struct drm_device* dev, struct mem_block*);
extern int nouveau_mem_init(struct drm_device *dev);
extern void nouveau_mem_close(struct drm_device *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
extern int nouveau_instmem_init(struct drm_device *dev);
Use nouveau_mem.c to allocate RAMIN.
2006-11-29 16:31:42 -07:00
extern struct mem_block* nouveau_instmem_alloc(struct drm_device *dev,
uint32_t size, uint32_t align);
extern void nouveau_instmem_free(struct drm_device *dev,
struct mem_block *block);
nouveau: map pci resource 2 on >=nv40
2007-01-07 05:56:45 -07:00
extern uint32_t nouveau_instmem_r32(drm_nouveau_private_t *dev_priv,
struct mem_block *mem, int index);
extern void nouveau_instmem_w32(drm_nouveau_private_t *dev_priv,
struct mem_block *mem, int index,
uint32_t val);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
/* nouveau_fifo.c */
Restructure initialisation a bit. - Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-13 14:11:49 -07:00
extern int nouveau_fifo_init(drm_device_t *dev);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
extern int nouveau_fifo_number(drm_device_t *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
extern int nouveau_fifo_ctx_size(drm_device_t *dev);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
extern void nouveau_fifo_cleanup(drm_device_t *dev, DRMFILE filp);
nouveau: support multiple channels per client (breaks drm interface)
2007-03-21 00:57:47 -06:00
extern int nouveau_fifo_owner(drm_device_t *dev, DRMFILE filp, int channel);
nouveau: Hook up grctx code for NV4x. This is enough to get grctx switching going on my NV40 and C51 after the binary driver has initialised the card first. Bumping the drm patchlevel because the ddx needs some modifications to have NV4x work at all with these changes.
2007-01-01 21:08:04 -07:00
extern void nouveau_fifo_free(drm_device_t *dev, int channel);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
/* nouveau_object.c */
nouveau: make sure cmdbuf object gets destroyed
2007-03-12 21:51:55 -06:00
extern void nouveau_object_cleanup(drm_device_t *dev, int channel);
nouveau: intrusive drm interface changes graphics objects: - No longer takes flags/dmaobj parameters, requires some major changes to the ddx to setup the object through the FIFO. This change is likely to cause breakages on some cards (tested on NV05,NV28,NV35, NV40 and NV4E). dma objects: - now takes a "class" parameter, not really used yet but we may need it at some point. - parameters are checked, so clients can't randomly create DMA objects pointing at whatever they feel like. misc: - Added FB_SIZE/AGP_SIZE getparams - Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR - Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't NOTIFICATION_PENDING.
2007-02-27 21:14:08 -07:00
extern struct nouveau_object *
nouveau: associate all created objects with a channel + cleanups
2007-03-12 21:18:03 -06:00
nouveau_object_gr_create(drm_device_t *dev, int channel, int class);
extern struct nouveau_object *
nouveau_object_dma_create(drm_device_t *dev, int channel, int class,
nouveau: intrusive drm interface changes graphics objects: - No longer takes flags/dmaobj parameters, requires some major changes to the ddx to setup the object through the FIFO. This change is likely to cause breakages on some cards (tested on NV05,NV28,NV35, NV40 and NV4E). dma objects: - now takes a "class" parameter, not really used yet but we may need it at some point. - parameters are checked, so clients can't randomly create DMA objects pointing at whatever they feel like. misc: - Added FB_SIZE/AGP_SIZE getparams - Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR - Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't NOTIFICATION_PENDING.
2007-02-27 21:14:08 -07:00
uint32_t offset, uint32_t size,
int access, int target);
nouveau: associate all created objects with a channel + cleanups
2007-03-12 21:18:03 -06:00
extern void nouveau_object_free(drm_device_t *dev, struct nouveau_object *obj);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
extern int nouveau_ioctl_object_init(DRM_IOCTL_ARGS);
extern int nouveau_ioctl_dma_object_init(DRM_IOCTL_ARGS);
Use nouveau_mem.c to allocate RAMIN.
2006-11-29 16:31:42 -07:00
extern uint32_t nouveau_chip_instance_get(drm_device_t *dev, struct mem_block *mem);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
/* nouveau_irq.c */
extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
extern void nouveau_irq_preinstall(drm_device_t*);
extern void nouveau_irq_postinstall(drm_device_t*);
extern void nouveau_irq_uninstall(drm_device_t*);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
/* nv04_fb.c */
extern int nv04_fb_init(drm_device_t *dev);
extern void nv04_fb_takedown(drm_device_t *dev);
/* nv10_fb.c */
extern int nv10_fb_init(drm_device_t *dev);
extern void nv10_fb_takedown(drm_device_t *dev);
/* nv40_fb.c */
extern int nv40_fb_init(drm_device_t *dev);
extern void nv40_fb_takedown(drm_device_t *dev);
nouveau: and of course, I was missing the last nv04 piece.
2007-02-02 22:13:27 -07:00
/* nv04_graph.c */
extern void nouveau_nv04_context_switch(drm_device_t *dev);
extern int nv04_graph_init(drm_device_t *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
extern void nv04_graph_takedown(drm_device_t *dev);
nouveau: and of course, I was missing the last nv04 piece.
2007-02-02 22:13:27 -07:00
extern int nv04_graph_context_create(drm_device_t *dev, int channel);
nouveau: first step to make graph ctx works It is still not working, but now we could use some 3D commands without needed to run nvidia blob before.
2007-01-13 13:43:47 -07:00
/* nv10_graph.c */
extern void nouveau_nv10_context_switch(drm_device_t *dev);
extern int nv10_graph_init(drm_device_t *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
extern void nv10_graph_takedown(drm_device_t *dev);
nouveau: first step to make graph ctx works It is still not working, but now we could use some 3D commands without needed to run nvidia blob before.
2007-01-13 13:43:47 -07:00
extern int nv10_graph_context_create(drm_device_t *dev, int channel);
nouveau: nv20 graph ctx switch. Untested...
2007-01-13 15:19:41 -07:00
/* nv20_graph.c */
extern void nouveau_nv20_context_switch(drm_device_t *dev);
extern int nv20_graph_init(drm_device_t *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
extern void nv20_graph_takedown(drm_device_t *dev);
nouveau: nv20 graph ctx switch. Untested...
2007-01-13 15:19:41 -07:00
extern int nv20_graph_context_create(drm_device_t *dev, int channel);
nouveau: get nv30 context switching to work. * Pulled in some registers from nv10reg.h. Needed for context switching. * Filled in nv30 graphics context (based on nv40_graph.c). * Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-11 22:13:05 -07:00
/* nv30_graph.c */
extern int nv30_graph_init(drm_device_t *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
extern void nv30_graph_takedown(drm_device_t *dev);
nouveau: get nv30 context switching to work. * Pulled in some registers from nv10reg.h. Needed for context switching. * Filled in nv30 graphics context (based on nv40_graph.c). * Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-11 22:13:05 -07:00
extern int nv30_graph_context_create(drm_device_t *dev, int channel);
nouveau: Add nv40-specific PGRAPH code, not hooked up yet.
2007-01-01 20:52:43 -07:00
/* nv40_graph.c */
extern int nv40_graph_init(drm_device_t *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
extern void nv40_graph_takedown(drm_device_t *dev);
nouveau: Add nv40-specific PGRAPH code, not hooked up yet.
2007-01-01 20:52:43 -07:00
extern int nv40_graph_context_create(drm_device_t *dev, int channel);
extern void nv40_graph_context_save_current(drm_device_t *dev);
extern void nv40_graph_context_restore(drm_device_t *dev, int channel);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
/* nv04_mc.c */
extern int nv04_mc_init(drm_device_t *dev);
extern void nv04_mc_takedown(drm_device_t *dev);
/* nv40_mc.c */
extern int nv40_mc_init(drm_device_t *dev);
extern void nv40_mc_takedown(drm_device_t *dev);
/* nv04_timer.c */
extern int nv04_timer_init(drm_device_t *dev);
extern void nv04_timer_takedown(drm_device_t *dev);
nouveau: add compat ioc32 support
2006-11-05 02:38:44 -07:00
extern long nouveau_compat_ioctl(struct file *filp, unsigned int cmd,
unsigned long arg);
add powerpc mmio swapper to NV_READ/WRITE macros
2006-11-05 01:46:53 -07:00
#if defined(__powerpc__)
#define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) )
#define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) )
#else
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
#define NV_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
#define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
add powerpc mmio swapper to NV_READ/WRITE macros
2006-11-05 01:46:53 -07:00
#endif
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
nouveau: map pci resource 2 on >=nv40
2007-01-07 05:56:45 -07:00
#define INSTANCE_WR(mem,ofs,val) nouveau_instmem_w32(dev_priv,(mem),(ofs),(val))
#define INSTANCE_RD(mem,ofs) nouveau_instmem_r32(dev_priv,(mem),(ofs))
Wrap access to objects in RAMIN. This will make it easier to support extra RAMIN in vram at a later point.
2006-11-29 14:35:42 -07:00
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
#endif /* __NOUVEAU_DRV_H__ */