Whitespace cleanups.
parent
c731b68091
commit
425da42e95
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@ -284,14 +284,16 @@ static bool intel_find_best_PLL(struct drm_crtc *crtc, int target,
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const intel_limit_t *limit = intel_limit(crtc);
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int err = target;
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if (IS_I9XX(dev)& intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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(I915_READ(LVDS) & LVDS_PORT_EN) != 0)
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{
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/* For LVDS, if the panel is on, just rely on its current settings for
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* dual-channel. We haven't figured out how to reliably set up
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* different single/dual channel state, if we even can.
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if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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(I915_READ(LVDS) & LVDS_PORT_EN) != 0) {
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/*
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* For LVDS, if the panel is on, just rely on its current
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* settings for dual-channel. We haven't figured out how to
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* reliably set up different single/dual channel state, if we
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* even can.
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*/
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if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
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if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
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LVDS_CLKB_POWER_UP)
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clock.p2 = limit->p2.p2_fast;
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else
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clock.p2 = limit->p2.p2_slow;
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@ -304,14 +306,13 @@ static bool intel_find_best_PLL(struct drm_crtc *crtc, int target,
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memset (best_clock, 0, sizeof (*best_clock));
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for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++)
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{
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for (clock.m2 = limit->m2.min; clock.m2 < clock.m1 && clock.m2 <= limit->m2.max; clock.m2++)
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{
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for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++)
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{
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for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max; clock.p1++)
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{
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for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
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for (clock.m2 = limit->m2.min; clock.m2 < clock.m1 &&
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clock.m2 <= limit->m2.max; clock.m2++) {
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for (clock.n = limit->n.min; clock.n <= limit->n.max;
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clock.n++) {
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for (clock.p1 = limit->p1.min;
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clock.p1 <= limit->p1.max; clock.p1++) {
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int this_err;
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intel_clock(dev, refclk, &clock);
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@ -328,6 +329,7 @@ static bool intel_find_best_PLL(struct drm_crtc *crtc, int target,
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}
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}
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}
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return (err != target);
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}
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