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R300+: fixup pixcache flush

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Alex Deucher 2008-05-12 09:30:47 -04:00
parent 3582e82f14
commit 5532b8d2a0
1 changed files with 28 additions and 8 deletions
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20
shared-core/radeon_cp.c
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@ -16222,6 +16222,7 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
tmp |= RADEON_RB3D_DC_FLUSH_ALL; tmp |= RADEON_RB3D_DC_FLUSH_ALL;
RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
@ -16233,6 +16234,25 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
} }
DRM_UDELAY(1); DRM_UDELAY(1);
} }
} else {
/* 3D */
tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
tmp |= RADEON_RB3D_DC_FLUSH_ALL;
RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
/* 2D */
tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
tmp |= RADEON_RB3D_DC_FLUSH_ALL;
RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
for (i = 0; i < dev_priv->usec_timeout; i++) {
if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
& RADEON_RB3D_DC_BUSY)) {
return 0;
}
DRM_UDELAY(1);
}
}
#if RADEON_FIFO_DEBUG #if RADEON_FIFO_DEBUG
DRM_ERROR("failed!\n"); DRM_ERROR("failed!\n");