amdgpu: add ras inject unit test
Both UMC and GFX ras single_correctable inject tests are added. Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>main
Guchun Chen
Alex Deucher
parent
018169bfba
commit
58fc6d6eae
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@ -30,7 +30,8 @@
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#include <fcntl.h>
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#include <stdio.h>
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#include "xf86drm.h"
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#include "stdlib.h"
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#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
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const char *ras_block_string[] = {
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"umc",
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@ -311,11 +312,10 @@ enum amdgpu_ras_error_type {
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AMDGPU_RAS_ERROR__POISON = 8,
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};
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struct ras_test_item {
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struct ras_inject_test_config {
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char name[64];
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int block;
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char block[32];
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int sub_block;
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char error_type_str[64];
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enum amdgpu_ras_error_type type;
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uint64_t address;
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uint64_t value;
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@ -390,12 +390,78 @@ struct ras_DID_test_mask{
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DEFAULT_RAS_BLOCK_MASK_BASIC\
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}
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static const struct ras_inject_test_config umc_ras_inject_test[] = {
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{"ras_umc.1.0", "umc", 0, AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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};
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static const struct ras_inject_test_config gfx_ras_inject_test[] = {
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{"ras_gfx.2.0", "gfx", AMDGPU_RAS_BLOCK__GFX_CPC_UCODE,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.1", "gfx", AMDGPU_RAS_BLOCK__GFX_CPF_TAG,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.2", "gfx", AMDGPU_RAS_BLOCK__GFX_CPG_TAG,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.3", "gfx", AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.4", "gfx", AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.5", "gfx", AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.6", "gfx", AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.7", "gfx", AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.8", "gfx", AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.9", "gfx", AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.10", "gfx", AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.11", "gfx", AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.12", "gfx", AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.13", "gfx", AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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{"ras_gfx.2.14", "gfx", AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM,
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AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0},
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};
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static const struct ras_DID_test_mask ras_DID_array[] = {
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{0x66a1, 0x00, RAS_BLOCK_MASK_ALL},
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{0x66a1, 0x01, RAS_BLOCK_MASK_ALL},
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{0x66a1, 0x04, RAS_BLOCK_MASK_ALL},
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};
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static uint32_t amdgpu_ras_find_block_id_by_name(const char *name)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
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if (strcmp(name, ras_block_string[i]) == 0)
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return i;
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}
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return ARRAY_SIZE(ras_block_string);
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}
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static char *amdgpu_ras_get_error_type_id(enum amdgpu_ras_error_type type)
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{
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switch (type) {
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case AMDGPU_RAS_ERROR__PARITY:
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return "parity";
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case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE:
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return "single_correctable";
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case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE:
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return "multi_uncorrectable";
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case AMDGPU_RAS_ERROR__POISON:
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return "poison";
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case AMDGPU_RAS_ERROR__NONE:
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default:
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return NULL;
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}
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}
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static struct ras_test_mask amdgpu_ras_get_test_mask(drmDevicePtr device)
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{
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int i;
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@ -775,43 +841,36 @@ static void amdgpu_ras_enable_test(void)
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}
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}
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static int amdgpu_ras_get_test_items(struct ras_test_item **pitems, int *size)
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static void __amdgpu_ras_ip_inject_test(const struct ras_inject_test_config *ip_test,
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uint32_t size)
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{
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*pitems = NULL;
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*size = 0;
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return 0;
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}
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static void __amdgpu_ras_inject_test(void)
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{
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struct ras_test_item *items = NULL;
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int i, size;
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int ret;
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int i, ret;
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unsigned long old_ue, old_ce;
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unsigned long ue, ce;
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uint32_t block;
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int timeout;
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bool pass;
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ret = amdgpu_ras_get_test_items(&items, &size);
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CU_ASSERT_EQUAL(ret, 0);
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if (ret)
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goto mem_free;
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printf("...\n");
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for (i = 0; i < size; i++) {
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timeout = 3;
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pass = false;
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ret = amdgpu_ras_query_err_count(items[i].block, &old_ue,
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&old_ce);
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block = amdgpu_ras_find_block_id_by_name(ip_test[i].block);
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/* Ensure one valid ip block */
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if (block == ARRAY_SIZE(ras_block_string))
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break;
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ret = amdgpu_ras_query_err_count(block, &old_ue, &old_ce);
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CU_ASSERT_EQUAL(ret, 0);
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if (ret)
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break;
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ret = amdgpu_ras_inject(items[i].block, items[i].sub_block,
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items[i].type, items[i].address,
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items[i].value);
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ret = amdgpu_ras_inject(block,
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ip_test[i].sub_block,
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ip_test[i].type,
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ip_test[i].address,
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ip_test[i].value);
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CU_ASSERT_EQUAL(ret, 0);
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if (ret)
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break;
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@ -819,8 +878,7 @@ static void __amdgpu_ras_inject_test(void)
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while (timeout > 0) {
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sleep(5);
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ret = amdgpu_ras_query_err_count(items[i].block, &ue,
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&ce);
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ret = amdgpu_ras_query_err_count(block, &ue, &ce);
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CU_ASSERT_EQUAL(ret, 0);
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if (ret)
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break;
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@ -832,16 +890,28 @@ static void __amdgpu_ras_inject_test(void)
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}
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timeout -= 1;
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}
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printf("\t Test %s@%s, address %ld, value %ld: %s\n",
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items[i].name, items[i].error_type_str, items[i].address,
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items[i].value, pass ? "Pass" : "Fail");
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printf("\t Test %s@block %s, subblock %d, error_type %s, address %ld, value %ld: %s\n",
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ip_test[i].name,
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ip_test[i].block,
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ip_test[i].sub_block,
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amdgpu_ras_get_error_type_id(ip_test[i].type),
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ip_test[i].address,
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ip_test[i].value,
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pass ? "Pass" : "Fail");
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}
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}
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mem_free:
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if (items) {
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free(items);
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items = NULL;
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}
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static void __amdgpu_ras_inject_test(void)
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{
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printf("...\n");
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/* run UMC ras inject test */
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__amdgpu_ras_ip_inject_test(umc_ras_inject_test,
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ARRAY_SIZE(umc_ras_inject_test));
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/* run GFX ras inject test */
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__amdgpu_ras_ip_inject_test(gfx_ras_inject_test,
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ARRAY_SIZE(gfx_ras_inject_test));
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}
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static void amdgpu_ras_inject_test(void)
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