copy over some files and reorg radeon to add ttm fencing not working yet
Dave Airlie
parent
223061e084
commit
be5bf1346e
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@ -27,7 +27,7 @@ nouveau-objs := nouveau_drv.o nouveau_state.o nouveau_fifo.o nouveau_mem.o \
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nv04_fb.o nv10_fb.o nv40_fb.o \
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nv04_graph.o nv10_graph.o nv20_graph.o nv30_graph.o \
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nv40_graph.o
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radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o
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radeon-objs := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o radeon_irq.o r300_cmdbuf.o radeon_fence.o radeon_buffer.o
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sis-objs := sis_drv.o sis_mm.o
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ffb-objs := ffb_drv.o ffb_context.o
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savage-objs := savage_drv.o savage_bci.o savage_state.o
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@ -0,0 +1,117 @@
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/**************************************************************************
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*
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* Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*
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**************************************************************************/
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/*
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* Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
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*/
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#include "drmP.h"
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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drm_ttm_backend_t *radeon_create_ttm_backend_entry(drm_device_t * dev)
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{
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return drm_agp_init_ttm(dev, NULL);
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}
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int radeon_fence_types(drm_buffer_object_t *bo, uint32_t * class, uint32_t * type)
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{
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*class = 0;
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if (bo->mem.flags & (DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE))
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*type = 3;
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else
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*type = 1;
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return 0;
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}
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int radeon_invalidate_caches(drm_device_t * dev, uint32_t flags)
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{
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/*
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* FIXME: Only emit once per batchbuffer submission.
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*/
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#if 0
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uint32_t flush_cmd = MI_NO_WRITE_FLUSH;
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if (flags & DRM_BO_FLAG_READ)
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flush_cmd |= MI_READ_FLUSH;
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if (flags & DRM_BO_FLAG_EXE)
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flush_cmd |= MI_EXE_FLUSH;
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return 0;
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// return radeon_emit_mi_flush(dev, flush_cmd);
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#endif
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return 0;
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}
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uint32_t radeon_evict_mask(drm_buffer_object_t *bo)
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{
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switch (bo->mem.mem_type) {
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case DRM_BO_MEM_LOCAL:
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case DRM_BO_MEM_TT:
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return DRM_BO_FLAG_MEM_LOCAL;
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default:
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return DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_CACHED;
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}
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}
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int radeon_init_mem_type(drm_device_t * dev, uint32_t type,
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drm_mem_type_manager_t * man)
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{
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switch (type) {
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case DRM_BO_MEM_LOCAL:
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man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
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_DRM_FLAG_MEMTYPE_CACHED;
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man->drm_bus_maptype = 0;
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break;
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case DRM_BO_MEM_TT:
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if (!(drm_core_has_AGP(dev) && dev->agp)) {
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DRM_ERROR("AGP is not enabled for memory type %u\n",
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(unsigned)type);
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return -EINVAL;
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}
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man->io_offset = dev->agp->agp_info.aper_base;
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man->io_size = dev->agp->agp_info.aper_size * 1024 * 1024;
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man->io_addr = NULL;
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man->flags = _DRM_FLAG_MEMTYPE_MAPPABLE |
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_DRM_FLAG_MEMTYPE_CSELECT | _DRM_FLAG_NEEDS_IOREMAP;
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man->drm_bus_maptype = _DRM_AGP;
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break;
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default:
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DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
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return -EINVAL;
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}
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return 0;
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}
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int radeon_move(drm_buffer_object_t * bo,
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int evict, int no_wait, drm_bo_mem_reg_t * new_mem)
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{
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return 0;
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}
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@ -56,6 +56,38 @@ static struct pci_device_id pciidlist[] = {
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radeon_PCI_IDS
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};
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#ifdef RADEON_HAVE_FENCE
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static drm_fence_driver_t radeon_fence_driver = {
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.num_classes = 1,
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.wrap_diff = (1 << 30),
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.flush_diff = (1 << 29),
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.sequence_mask = 0xffffffffU,
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.lazy_capable = 1,
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.emit = radeon_fence_emit_sequence,
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.poke_flush = radeon_poke_flush,
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.has_irq = radeon_fence_has_irq,
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};
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#endif
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#ifdef RADEON_HAVE_BUFFER
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static uint32_t radeon_mem_prios[] = {DRM_BO_MEM_PRIV0, DRM_BO_MEM_TT, DRM_BO_MEM_LOCAL};
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static uint32_t radeon_busy_prios[] = {DRM_BO_MEM_TT, DRM_BO_MEM_PRIV0, DRM_BO_MEM_LOCAL};
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static drm_bo_driver_t radeon_bo_driver = {
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.mem_type_prio = radeon_mem_prios,
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.mem_busy_prio = radeon_busy_prios,
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.num_mem_type_prio = sizeof(radeon_mem_prios)/sizeof(uint32_t),
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.num_mem_busy_prio = sizeof(radeon_busy_prios)/sizeof(uint32_t),
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.create_ttm_backend_entry = radeon_create_ttm_backend_entry,
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.fence_type = radeon_fence_types,
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.invalidate_caches = radeon_invalidate_caches,
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.init_mem_type = radeon_init_mem_type,
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.evict_mask = radeon_evict_mask,
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.move = radeon_move,
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};
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#endif
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static int probe(struct pci_dev *pdev, const struct pci_device_id *ent);
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static struct drm_driver driver = {
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.driver_features =
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@ -100,6 +132,13 @@ static struct drm_driver driver = {
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.remove = __devexit_p(drm_cleanup_pci),
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},
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#ifdef RADEON_HAVE_FENCE
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.fence_driver = &radeon_fence_driver,
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#endif
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#ifdef RADEON_HAVE_BUFFER
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.bo_driver = &radeon_bo_driver,
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#endif
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.name = DRIVER_NAME,
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.desc = DRIVER_DESC,
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.date = DRIVER_DATE,
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@ -0,0 +1,128 @@
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/**************************************************************************
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*
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* Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*
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**************************************************************************/
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/*
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* Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "radeon_drm.h"
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#include "radeon_drv.h"
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/*
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* Implements an intel sync flush operation.
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*/
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static void radeon_perform_flush(drm_device_t * dev)
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{
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drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
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drm_fence_manager_t *fm = &dev->fm;
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drm_fence_class_manager_t *fc = &dev->fm.class[0];
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drm_fence_driver_t *driver = dev->driver->fence_driver;
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uint32_t pending_flush_types = 0;
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uint32_t flush_flags = 0;
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uint32_t flush_sequence = 0;
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uint32_t i_status;
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uint32_t diff;
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uint32_t sequence;
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if (!dev_priv)
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return;
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pending_flush_types = fc->pending_flush |
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((fc->pending_exe_flush) ? DRM_FENCE_TYPE_EXE : 0);
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if (pending_flush_types) {
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drm_fence_handler(dev, 0, 0,0);
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}
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return;
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}
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void radeon_poke_flush(drm_device_t * dev, uint32_t class)
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{
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drm_fence_manager_t *fm = &dev->fm;
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unsigned long flags;
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if (class != 0)
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return;
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write_lock_irqsave(&fm->lock, flags);
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radeon_perform_flush(dev);
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write_unlock_irqrestore(&fm->lock, flags);
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}
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int radeon_fence_emit_sequence(drm_device_t *dev, uint32_t class,
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uint32_t flags, uint32_t *sequence,
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uint32_t *native_type)
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{
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drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
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RING_LOCALS;
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if (!dev_priv)
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return -EINVAL;
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*native_type = DRM_FENCE_TYPE_EXE;
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if (flags & DRM_RADEON_FENCE_FLAG_FLUSHED) {
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*native_type |= DRM_RADEON_FENCE_TYPE_RW;
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BEGIN_RING(4);
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RADEON_FLUSH_CACHE();
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RADEON_FLUSH_ZCACHE();
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ADVANCE_RING();
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}
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radeon_emit_irq(dev);
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*sequence = (uint32_t) dev_priv->counter;
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return 0;
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}
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void radeon_fence_handler(drm_device_t * dev)
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{
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drm_fence_manager_t *fm = &dev->fm;
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write_lock(&fm->lock);
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radeon_perform_flush(dev);
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write_unlock(&fm->lock);
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}
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int radeon_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags)
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{
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/*
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* We have an irq that tells us when we have a new breadcrumb.
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*/
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if (class == 0 && flags == DRM_FENCE_TYPE_EXE)
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return 1;
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return 0;
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}
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@ -434,8 +434,17 @@ typedef struct {
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int pfCurrentPage; /* which buffer is being displayed? */
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int crtc2_base; /* CRTC2 frame offset */
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int tiling_enabled; /* set by drm, read by 2d + 3d clients */
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unsigned int last_fence;
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} drm_radeon_sarea_t;
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/* The only fence class we support */
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#define DRM_RADEON_FENCE_CLASS_ACCEL 0
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/* Fence type that guarantees read-write flush */
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#define DRM_RADEON_FENCE_TYPE_RW 2
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/* cache flushes programmed just before the fence */
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#define DRM_RADEON_FENCE_FLAG_FLUSHED 0x01000000
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/* WARNING: If you change any of these defines, make sure to change the
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* defines in the Xserver file (xf86drmRadeon.h)
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*
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@ -102,6 +102,11 @@
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#define DRIVER_MINOR 26
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#define DRIVER_PATCHLEVEL 0
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#if defined(__linux__)
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#define RADEON_HAVE_FENCE
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#define RADEON_HAVE_BUFFER
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#endif
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/*
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* Radeon chip families
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*/
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@ -276,8 +281,8 @@ typedef struct drm_radeon_private {
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struct mem_block *fb_heap;
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/* SW interrupt */
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wait_queue_head_t swi_queue;
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atomic_t swi_emitted;
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wait_queue_head_t irq_queue;
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int counter;
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struct radeon_surface surfaces[RADEON_MAX_SURFACES];
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struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES];
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@ -376,6 +381,30 @@ extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp,
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drm_file_t* filp_priv,
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drm_radeon_kcmd_buffer_t* cmdbuf);
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#ifdef RADEON_HAVE_FENCE
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/* i915_fence.c */
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extern void radeon_fence_handler(drm_device_t *dev);
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extern int radeon_fence_emit_sequence(drm_device_t *dev, uint32_t class,
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uint32_t flags, uint32_t *sequence,
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uint32_t *native_type);
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extern void radeon_poke_flush(drm_device_t *dev, uint32_t class);
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extern int radeon_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags);
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#endif
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#ifdef RADEON_HAVE_BUFFER
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/* radeon_buffer.c */
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extern drm_ttm_backend_t *radeon_create_ttm_backend_entry(drm_device_t *dev);
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extern int radeon_fence_types(struct drm_buffer_object *bo, uint32_t *class, uint32_t *type);
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extern int radeon_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags);
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extern uint32_t radeon_evict_mask(drm_buffer_object_t *bo);
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extern int radeon_init_mem_type(drm_device_t * dev, uint32_t type,
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drm_mem_type_manager_t * man);
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extern int radeon_move(drm_buffer_object_t * bo,
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int evict, int no_wait, drm_bo_mem_reg_t * new_mem);
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#endif
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/* Flags for stats.boxes
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*/
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#define RADEON_BOX_DMA_IDLE 0x1
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@ -1184,4 +1213,19 @@ do { \
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write &= mask; \
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} while (0)
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/* Breadcrumb - swi irq */
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#define READ_BREADCRUMB(dev_priv) RADEON_READ(RADEON_LAST_SWI_REG)
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static inline int radeon_update_breadcrumb(drm_device_t *dev)
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{
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drm_radeon_private_t *dev_priv = dev->dev_private;
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dev_priv->sarea_priv->last_fence = ++dev_priv->counter;
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if (dev_priv->counter > 0x7FFFFFFFUL)
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dev_priv->sarea_priv->last_fence = dev_priv->counter = 1;
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return dev_priv->counter;
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}
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#endif /* __RADEON_DRV_H__ */
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@ -79,7 +79,10 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
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/* SW interrupt */
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if (stat & RADEON_SW_INT_TEST) {
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DRM_WAKEUP(&dev_priv->swi_queue);
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DRM_WAKEUP(&dev_priv->irq_queue);
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#ifdef RADEON_HAVE_FENCE
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radeon_fence_handler(dev);
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#endif
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}
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/* VBLANK interrupt */
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@ -98,8 +101,7 @@ static int radeon_emit_irq(drm_device_t * dev)
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unsigned int ret;
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RING_LOCALS;
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atomic_inc(&dev_priv->swi_emitted);
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ret = atomic_read(&dev_priv->swi_emitted);
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ret = radeon_update_breadcrumb(dev);
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BEGIN_RING(4);
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OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
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@ -110,19 +112,19 @@ static int radeon_emit_irq(drm_device_t * dev)
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return ret;
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}
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static int radeon_wait_irq(drm_device_t * dev, int swi_nr)
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static int radeon_wait_irq(drm_device_t * dev, int irq_nr)
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{
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drm_radeon_private_t *dev_priv =
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(drm_radeon_private_t *) dev->dev_private;
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int ret = 0;
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if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
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if (READ_BREADCRUMB(dev_priv) >= irq_nr)
|
||||
return 0;
|
||||
|
||||
dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
|
||||
|
||||
DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
|
||||
RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
|
||||
DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
|
||||
READ_BREADCRUMB(dev_priv) >= irq_nr);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -224,8 +226,8 @@ void radeon_driver_irq_postinstall(drm_device_t * dev)
|
|||
drm_radeon_private_t *dev_priv =
|
||||
(drm_radeon_private_t *) dev->dev_private;
|
||||
|
||||
atomic_set(&dev_priv->swi_emitted, 0);
|
||||
DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
|
||||
dev_priv->counter = 0;
|
||||
DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
|
||||
|
||||
/* Turn on SW and VBL ints */
|
||||
RADEON_WRITE(RADEON_GEN_INT_CNTL,
|
||||
|
|
|
|||
Loading…
Reference in New Issue