tests/amdgpu: add memcpy dispatch test
add memcpy dispatch test for gfx9 Signed-off-by: Flora Cui <flora.cui@amd.com> Tested-by: Rui Teng <rui.teng@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>main
parent
8db4e2db41
commit
c1ced0bafd
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@ -294,6 +294,7 @@ static uint32_t shader_bin[] = {
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enum cs_type {
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enum cs_type {
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CS_BUFFERCLEAR,
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CS_BUFFERCLEAR,
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CS_BUFFERCOPY
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};
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};
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static const uint32_t bufferclear_cs_shader_gfx9[] = {
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static const uint32_t bufferclear_cs_shader_gfx9[] = {
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@ -312,6 +313,11 @@ static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = {
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static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5;
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static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5;
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static const uint32_t buffercopy_cs_shader_gfx9[] = {
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0xD1FD0000, 0x04010C08, 0xE00C2000, 0x80000100,
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0xBF8C0F70, 0xE01C2000, 0x80010100, 0xBF810000
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};
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int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
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int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
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unsigned alignment, unsigned heap, uint64_t alloc_flags,
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unsigned alignment, unsigned heap, uint64_t alloc_flags,
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uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
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uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu,
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@ -1920,6 +1926,10 @@ static int amdgpu_dispatch_load_cs_shader(uint8_t *ptr,
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shader = bufferclear_cs_shader_gfx9;
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shader = bufferclear_cs_shader_gfx9;
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shader_size = sizeof(bufferclear_cs_shader_gfx9);
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shader_size = sizeof(bufferclear_cs_shader_gfx9);
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break;
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break;
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case CS_BUFFERCOPY:
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shader = buffercopy_cs_shader_gfx9;
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shader_size = sizeof(buffercopy_cs_shader_gfx9);
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break;
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default:
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default:
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return -1;
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return -1;
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break;
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break;
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@ -2134,6 +2144,151 @@ static void amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
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CU_ASSERT_EQUAL(r, 0);
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CU_ASSERT_EQUAL(r, 0);
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}
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}
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void amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
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uint32_t ip_type,
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uint32_t ring)
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{
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amdgpu_context_handle context_handle;
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amdgpu_bo_handle bo_src, bo_dst, bo_shader, bo_cmd, resources[4];
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volatile unsigned char *ptr_dst;
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void *ptr_shader;
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unsigned char *ptr_src;
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uint32_t *ptr_cmd;
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uint64_t mc_address_src, mc_address_dst, mc_address_shader, mc_address_cmd;
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amdgpu_va_handle va_src, va_dst, va_shader, va_cmd;
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int i, r;
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int bo_dst_size = 16384;
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int bo_shader_size = 4096;
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int bo_cmd_size = 4096;
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struct amdgpu_cs_request ibs_request = {0};
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struct amdgpu_cs_ib_info ib_info= {0};
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uint32_t expired;
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amdgpu_bo_list_handle bo_list;
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struct amdgpu_cs_fence fence_status = {0};
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r = amdgpu_cs_ctx_create(device_handle, &context_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_cmd_size, 4096,
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AMDGPU_GEM_DOMAIN_GTT, 0,
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&bo_cmd, (void **)&ptr_cmd,
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&mc_address_cmd, &va_cmd);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
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AMDGPU_GEM_DOMAIN_VRAM, 0,
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&bo_shader, &ptr_shader,
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&mc_address_shader, &va_shader);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCOPY );
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
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AMDGPU_GEM_DOMAIN_VRAM, 0,
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&bo_src, (void **)&ptr_src,
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&mc_address_src, &va_src);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
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AMDGPU_GEM_DOMAIN_VRAM, 0,
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&bo_dst, (void **)&ptr_dst,
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&mc_address_dst, &va_dst);
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CU_ASSERT_EQUAL(r, 0);
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memset(ptr_src, 0x55, bo_dst_size);
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i = 0;
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i += amdgpu_dispatch_init(ptr_cmd + i, ip_type);
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/* Issue commands to set cu mask used in current dispatch */
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i += amdgpu_dispatch_write_cumask(ptr_cmd + i);
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/* Writes shader state to HW */
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i += amdgpu_dispatch_write2hw(ptr_cmd + i, mc_address_shader);
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/* Write constant data */
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/* Writes the texture resource constants data to the SGPRs */
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ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
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ptr_cmd[i++] = 0x240;
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ptr_cmd[i++] = mc_address_src;
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ptr_cmd[i++] = (mc_address_src >> 32) | 0x100000;
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ptr_cmd[i++] = 0x400;
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ptr_cmd[i++] = 0x74fac;
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/* Writes the UAV constant data to the SGPRs. */
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ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
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ptr_cmd[i++] = 0x244;
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ptr_cmd[i++] = mc_address_dst;
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ptr_cmd[i++] = (mc_address_dst >> 32) | 0x100000;
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ptr_cmd[i++] = 0x400;
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ptr_cmd[i++] = 0x74fac;
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/* dispatch direct command */
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ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
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ptr_cmd[i++] = 0x10;
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ptr_cmd[i++] = 1;
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ptr_cmd[i++] = 1;
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ptr_cmd[i++] = 1;
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while (i & 7)
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ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */
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resources[0] = bo_shader;
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resources[1] = bo_src;
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resources[2] = bo_dst;
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resources[3] = bo_cmd;
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r = amdgpu_bo_list_create(device_handle, 4, resources, NULL, &bo_list);
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CU_ASSERT_EQUAL(r, 0);
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ib_info.ib_mc_address = mc_address_cmd;
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ib_info.size = i;
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ibs_request.ip_type = ip_type;
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ibs_request.ring = ring;
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ibs_request.resources = bo_list;
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ibs_request.number_of_ibs = 1;
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ibs_request.ibs = &ib_info;
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ibs_request.fence_info.handle = NULL;
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r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
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CU_ASSERT_EQUAL(r, 0);
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fence_status.ip_type = ip_type;
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fence_status.ip_instance = 0;
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fence_status.ring = ring;
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fence_status.context = context_handle;
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fence_status.fence = ibs_request.seq_no;
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/* wait for IB accomplished */
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r = amdgpu_cs_query_fence_status(&fence_status,
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AMDGPU_TIMEOUT_INFINITE,
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0, &expired);
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CU_ASSERT_EQUAL(r, 0);
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CU_ASSERT_EQUAL(expired, true);
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/* verify if memcpy test result meets with expected */
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i = 0;
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while(i < bo_dst_size) {
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CU_ASSERT_EQUAL(ptr_dst[i], ptr_src[i]);
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i++;
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}
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r = amdgpu_bo_list_destroy(bo_list);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_unmap_and_free(bo_src, va_src, mc_address_src, bo_dst_size);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_dst_size);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_unmap_and_free(bo_cmd, va_cmd, mc_address_cmd, bo_cmd_size);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_unmap_and_free(bo_shader, va_shader, mc_address_shader, bo_shader_size);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_cs_ctx_free(context_handle);
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CU_ASSERT_EQUAL(r, 0);
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}
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static void amdgpu_dispatch_test(void)
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static void amdgpu_dispatch_test(void)
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{
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{
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int r;
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int r;
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@ -2143,12 +2298,16 @@ static void amdgpu_dispatch_test(void)
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r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, &info);
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r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, &info);
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CU_ASSERT_EQUAL(r, 0);
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CU_ASSERT_EQUAL(r, 0);
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for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++)
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for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
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amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id);
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amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id);
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amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_COMPUTE, ring_id);
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}
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r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
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r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info);
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CU_ASSERT_EQUAL(r, 0);
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CU_ASSERT_EQUAL(r, 0);
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for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++)
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for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
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amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id);
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amdgpu_memset_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id);
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amdgpu_memcpy_dispatch_test(device_handle, AMDGPU_HW_IP_GFX, ring_id);
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}
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}
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}
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