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nouveau: funcs to determine active channel on PFIFO.

main
Ben Skeggs 2007-11-14 03:27:37 +11:00
parent 793cd1dad5
commit d0904f0f2b
12 changed files with 87 additions and 38 deletions
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8
shared-core/nouveau_drv.h
View File

@ -193,9 +193,13 @@ struct nouveau_fb_engine {
struct nouveau_fifo_engine {
void *priv;
int channels;
int (*init)(struct drm_device *);
void (*takedown)(struct drm_device *);
int (*channel_id)(struct drm_device *);
int (*create_context)(struct nouveau_channel *);
void (*destroy_context)(struct nouveau_channel *);
int (*load_context)(struct nouveau_channel *);
@ -364,7 +368,6 @@ extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
/* nouveau_fifo.c */
extern int nouveau_fifo_init(struct drm_device *);
extern int nouveau_fifo_number(struct drm_device *);
extern int nouveau_fifo_ctx_size(struct drm_device *);
extern void nouveau_fifo_cleanup(struct drm_device *, struct drm_file *);
extern int nouveau_fifo_owner(struct drm_device *, struct drm_file *,
@ -452,12 +455,14 @@ extern int nv40_fb_init(struct drm_device *);
extern void nv40_fb_takedown(struct drm_device *);
/* nv04_fifo.c */
extern int nv04_fifo_channel_id(struct drm_device *);
extern int nv04_fifo_create_context(struct nouveau_channel *);
extern void nv04_fifo_destroy_context(struct nouveau_channel *);
extern int nv04_fifo_load_context(struct nouveau_channel *);
extern int nv04_fifo_save_context(struct nouveau_channel *);
/* nv10_fifo.c */
extern int nv10_fifo_channel_id(struct drm_device *);
extern int nv10_fifo_create_context(struct nouveau_channel *);
extern void nv10_fifo_destroy_context(struct nouveau_channel *);
extern int nv10_fifo_load_context(struct nouveau_channel *);
@ -473,6 +478,7 @@ extern int nv40_fifo_save_context(struct nouveau_channel *);
/* nv50_fifo.c */
extern int nv50_fifo_init(struct drm_device *);
extern void nv50_fifo_takedown(struct drm_device *);
extern int nv50_fifo_channel_id(struct drm_device *);
extern int nv50_fifo_create_context(struct nouveau_channel *);
extern void nv50_fifo_destroy_context(struct nouveau_channel *);
extern int nv50_fifo_load_context(struct nouveau_channel *);

27
shared-core/nouveau_fifo.c
View File

@ -28,22 +28,6 @@
#include "nouveau_drm.h"
/* returns the number of hw fifos */
int nouveau_fifo_number(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv=dev->dev_private;
switch(dev_priv->card_type)
{
case NV_04:
case NV_05:
return 16;
case NV_50:
return 128;
default:
return 32;
}
}
/* returns the size of fifo context */
int nouveau_fifo_ctx_size(struct drm_device *dev)
{
@ -288,12 +272,13 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
* (woo, full userspace command submission !)
* When there are no more contexts, you lost
*/
for(channel=0; channel<nouveau_fifo_number(dev); channel++) {
for (channel = 0; channel < engine->fifo.channels; channel++) {
if (dev_priv->fifos[channel] == NULL)
break;
}
/* no more fifos. you lost. */
if (channel==nouveau_fifo_number(dev))
if (channel == engine->fifo.channels)
return -EINVAL;
dev_priv->fifos[channel] = drm_calloc(1, sizeof(struct nouveau_channel),
@ -451,10 +436,11 @@ void nouveau_fifo_free(struct nouveau_channel *chan)
void nouveau_fifo_cleanup(struct drm_device *dev, struct drm_file *file_priv)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_engine *engine = &dev_priv->Engine;
int i;
DRM_DEBUG("clearing FIFO enables from file_priv\n");
for(i = 0; i < nouveau_fifo_number(dev); i++) {
for(i = 0; i < engine->fifo.channels; i++) {
struct nouveau_channel *chan = dev_priv->fifos[i];
if (chan && chan->file_priv == file_priv)
@ -467,8 +453,9 @@ nouveau_fifo_owner(struct drm_device *dev, struct drm_file *file_priv,
int channel)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_engine *engine = &dev_priv->Engine;
if (channel >= nouveau_fifo_number(dev))
if (channel >= engine->fifo.channels)
return 0;
if (dev_priv->fifos[channel] == NULL)
return 0;

11
shared-core/nouveau_irq.c
View File

@ -68,6 +68,7 @@ static void
nouveau_fifo_irq_handler(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_engine *engine = &dev_priv->Engine;
uint32_t status;
while ((status = NV_READ(NV03_PFIFO_INTR_0))) {
@ -75,8 +76,7 @@ nouveau_fifo_irq_handler(struct drm_device *dev)
NV_WRITE(NV03_PFIFO_CACHES, 0);
chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
(nouveau_fifo_number(dev) - 1);
chid = engine->fifo.channel_id(dev);
get = NV_READ(NV03_PFIFO_CACHE1_GET);
if (status & NV_PFIFO_INTR_CACHE_ERROR) {
@ -190,6 +190,7 @@ static int
nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_engine *engine = &dev_priv->Engine;
int channel;
if (dev_priv->card_type < NV_10) {
@ -234,8 +235,7 @@ nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
}
}
if (channel > nouveau_fifo_number(dev) ||
dev_priv->fifos[channel] == NULL) {
if (channel > engine->fifo.channels || !dev_priv->fifos[channel]) {
DRM_ERROR("AIII, invalid/inactive channel id %d\n", channel);
return -EINVAL;
}
@ -365,9 +365,10 @@ static inline void
nouveau_pgraph_intr_context_switch(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_engine *engine = &dev_priv->Engine;
uint32_t chid;
chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1);
chid = engine->fifo.channel_id(dev);
DRM_DEBUG("PGRAPH context switch interrupt channel %x\n", chid);
switch(dev_priv->card_type) {

5
shared-core/nouveau_reg.h
View File

@ -406,6 +406,11 @@
#define NV04_PFIFO_CACHE0_PULL1 0x00003054
#define NV03_PFIFO_CACHE1_PUSH0 0x00003200
#define NV03_PFIFO_CACHE1_PUSH1 0x00003204
#define NV03_PFIFO_CACHE1_PUSH1_DMA (1<<8)
#define NV40_PFIFO_CACHE1_PUSH1_DMA (1<<16)
#define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f
#define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f
#define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f
#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220
#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224
# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000

12
shared-core/nouveau_state.c
View File

@ -116,8 +116,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->graph.destroy_context = nv04_graph_destroy_context;
engine->graph.load_context = nv04_graph_load_context;
engine->graph.save_context = nv04_graph_save_context;
engine->fifo.channels = 16;
engine->fifo.init = nouveau_fifo_init;
engine->fifo.takedown = nouveau_stub_takedown;
engine->fifo.channel_id = nv04_fifo_channel_id;
engine->fifo.create_context = nv04_fifo_create_context;
engine->fifo.destroy_context = nv04_fifo_destroy_context;
engine->fifo.load_context = nv04_fifo_load_context;
@ -143,8 +145,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->graph.destroy_context = nv10_graph_destroy_context;
engine->graph.load_context = nv10_graph_load_context;
engine->graph.save_context = nv10_graph_save_context;
engine->fifo.channels = 32;
engine->fifo.init = nouveau_fifo_init;
engine->fifo.takedown = nouveau_stub_takedown;
engine->fifo.channel_id = nv10_fifo_channel_id;
engine->fifo.create_context = nv10_fifo_create_context;
engine->fifo.destroy_context = nv10_fifo_destroy_context;
engine->fifo.load_context = nv10_fifo_load_context;
@ -170,8 +174,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->graph.destroy_context = nv20_graph_destroy_context;
engine->graph.load_context = nv20_graph_load_context;
engine->graph.save_context = nv20_graph_save_context;
engine->fifo.channels = 32;
engine->fifo.init = nouveau_fifo_init;
engine->fifo.takedown = nouveau_stub_takedown;
engine->fifo.channel_id = nv10_fifo_channel_id;
engine->fifo.create_context = nv10_fifo_create_context;
engine->fifo.destroy_context = nv10_fifo_destroy_context;
engine->fifo.load_context = nv10_fifo_load_context;
@ -197,8 +203,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->graph.destroy_context = nv20_graph_destroy_context;
engine->graph.load_context = nv20_graph_load_context;
engine->graph.save_context = nv20_graph_save_context;
engine->fifo.channels = 32;
engine->fifo.init = nouveau_fifo_init;
engine->fifo.takedown = nouveau_stub_takedown;
engine->fifo.channel_id = nv10_fifo_channel_id;
engine->fifo.create_context = nv10_fifo_create_context;
engine->fifo.destroy_context = nv10_fifo_destroy_context;
engine->fifo.load_context = nv10_fifo_load_context;
@ -224,8 +232,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->graph.destroy_context = nv40_graph_destroy_context;
engine->graph.load_context = nv40_graph_load_context;
engine->graph.save_context = nv40_graph_save_context;
engine->fifo.channels = 32;
engine->fifo.init = nv40_fifo_init;
engine->fifo.takedown = nouveau_stub_takedown;
engine->fifo.channel_id = nv10_fifo_channel_id;
engine->fifo.create_context = nv40_fifo_create_context;
engine->fifo.destroy_context = nv40_fifo_destroy_context;
engine->fifo.load_context = nv40_fifo_load_context;
@ -252,8 +262,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
engine->graph.destroy_context = nv50_graph_destroy_context;
engine->graph.load_context = nv50_graph_load_context;
engine->graph.save_context = nv50_graph_save_context;
engine->fifo.channels = 128;
engine->fifo.init = nv50_fifo_init;
engine->fifo.takedown = nv50_fifo_takedown;
engine->fifo.channel_id = nv50_fifo_channel_id;
engine->fifo.create_context = nv50_fifo_create_context;
engine->fifo.destroy_context = nv50_fifo_destroy_context;
engine->fifo.load_context = nv50_fifo_load_context;

12
shared-core/nv04_fifo.c
View File

@ -35,6 +35,15 @@
#define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE))
#define NV04_RAMFC__SIZE 32
int
nv04_fifo_channel_id(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
NV03_PFIFO_CACHE1_PUSH1_CHID_MASK);
}
int
nv04_fifo_create_context(struct nouveau_channel *chan)
{
@ -84,7 +93,8 @@ nv04_fifo_load_context(struct nouveau_channel *chan)
struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t tmp;
NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | chan->id);
NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,
NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET));
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT));

5
shared-core/nv04_graph.c
View File

@ -353,6 +353,7 @@ struct graph_state {
void nouveau_nv04_context_switch(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_engine *engine = &dev_priv->Engine;
struct nouveau_channel *next, *last;
int chid;
@ -370,7 +371,7 @@ void nouveau_nv04_context_switch(struct drm_device *dev)
return;
}
chid = NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
chid = engine->fifo.channel_id(dev);
next = dev_priv->fifos[chid];
if (!next) {
@ -378,7 +379,7 @@ void nouveau_nv04_context_switch(struct drm_device *dev)
return;
}
chid = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
chid = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (engine->fifo.channels - 1);
last = dev_priv->fifos[chid];
if (!last) {

9
shared-core/nv04_instmem.c
View File

@ -33,6 +33,7 @@ static void
nv04_instmem_configure_fixed_tables(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_engine *engine = &dev_priv->Engine;
/* FIFO hash table (RAMHT)
* use 4k hash table at RAMIN+0x10000
@ -61,8 +62,8 @@ nv04_instmem_configure_fixed_tables(struct drm_device *dev)
case NV_40:
case NV_44:
dev_priv->ramfc_offset = 0x20000;
dev_priv->ramfc_size = nouveau_fifo_number(dev) *
nouveau_fifo_ctx_size(dev);
dev_priv->ramfc_size = engine->fifo.channels *
nouveau_fifo_ctx_size(dev);
break;
case NV_30:
case NV_20:
@ -72,8 +73,8 @@ nv04_instmem_configure_fixed_tables(struct drm_device *dev)
case NV_04:
default:
dev_priv->ramfc_offset = 0x11400;
dev_priv->ramfc_size = nouveau_fifo_number(dev) *
nouveau_fifo_ctx_size(dev);
dev_priv->ramfc_size = engine->fifo.channels *
nouveau_fifo_ctx_size(dev);
break;
}
DRM_DEBUG("RAMFC offset=0x%x, size=%d\n", dev_priv->ramfc_offset,

12
shared-core/nv10_fifo.c
View File

@ -36,6 +36,15 @@
#define NV10_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV10_RAMFC__SIZE))
#define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)
int
nv10_fifo_channel_id(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
NV10_PFIFO_CACHE1_PUSH1_CHID_MASK);
}
int
nv10_fifo_create_context(struct nouveau_channel *chan)
{
@ -87,7 +96,8 @@ nv10_fifo_load_context(struct nouveau_channel *chan)
struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t tmp;
NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00000100 | chan->id);
NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,
NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET , RAMFC_RD(DMA_GET));
NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT , RAMFC_RD(DMA_PUT));

11
shared-core/nv10_graph.c
View File

@ -692,6 +692,7 @@ int nv10_graph_save_context(struct nouveau_channel *chan)
void nouveau_nv10_context_switch(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv;
struct nouveau_engine *engine;
struct nouveau_channel *next, *last;
int chid;
@ -708,8 +709,10 @@ void nouveau_nv10_context_switch(struct drm_device *dev)
DRM_DEBUG("Invalid drm_nouveau_private->fifos\n");
return;
}
engine = &dev_priv->Engine;
chid = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20)&(nouveau_fifo_number(dev)-1);
chid = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) &
(engine->fifo.channels - 1);
next = dev_priv->fifos[chid];
if (!next) {
@ -717,7 +720,8 @@ void nouveau_nv10_context_switch(struct drm_device *dev)
return;
}
chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) &
(engine->fifo.channels - 1);
last = dev_priv->fifos[chid];
if (!last) {
@ -827,13 +831,14 @@ void nv10_graph_destroy_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_engine *engine = &dev_priv->Engine;
struct graph_state* pgraph_ctx = chan->pgraph_ctx;
int chid;
drm_free(pgraph_ctx, sizeof(*pgraph_ctx), DRM_MEM_DRIVER);
chan->pgraph_ctx = NULL;
chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
chid = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (engine->fifo.channels - 1);
/* This code seems to corrupt the 3D pipe, but blob seems to do similar things ????
*/

4
shared-core/nv40_fifo.c
View File

@ -135,7 +135,9 @@ nv40_fifo_load_context(struct nouveau_channel *chan)
NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, tmp);
/* Set channel active, and in DMA mode */
NV_WRITE(NV03_PFIFO_CACHE1_PUSH1 , 0x00010000 | chan->id);
NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,
NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
/* Reset DMA_CTL_AT_INFO to INVALID */
tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);

9
shared-core/nv50_fifo.c
View File

@ -212,6 +212,15 @@ nv50_fifo_takedown(struct drm_device *dev)
drm_free(priv, sizeof(*priv), DRM_MEM_DRIVER);
}
int
nv50_fifo_channel_id(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
NV50_PFIFO_CACHE1_PUSH1_CHID_MASK);
}
int
nv50_fifo_create_context(struct nouveau_channel *chan)
{