Commit Graph

351 Commits (0f2f38bf06ad6211fdfb07e5a4edace07e86f0fc)

Author SHA1 Message Date
Emil Velikov 86326a2c53 intel: include i915_pciids.h in the tarball
Fixes: 4e81d4f9c9 ("intel: add generic functions to check PCI ID")
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2018-10-04 15:22:30 +01:00
Emil Velikov 99c3540dd4 *-symbols-check: error out when using unset variables
It will make bugs like the one fixed with previous patch dead obvious.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-04 14:39:27 +01:00
Emil Velikov 660643e498 automake: set NM before running the tests
Set/export the NM variable since it may not be set already.

Fixes: 4f08bfe96d ("*-symbol-check: Don't hard-code nm executable")
Cc: Heiko Becker <heirecka@exherbo.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-10-04 14:39:06 +01:00
Eric Engestrom a2920ea6a8 intel: add missing drm_public exports
Fixes: 36bb0ea47b "intel: annotate public functions"
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108006
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Dylan Baker <dylan@pnwbakers.com>
2018-09-20 18:23:19 +01:00
Lucas De Marchi 1e3fcc495b autotools: make symbols hidden by default
Now that symbols that should be exported are annotated accordingly, make
all the rest hidden by default.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi ba808253bc meson: make symbols hidden by default
Now that symbols that should be exported are annotated accordingly, make
all the rest hidden by default.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:45 -07:00
Lucas De Marchi 36bb0ea47b intel: annotate public functions
This was done with:
while read sym; do
	read f func line _ <<<$(cscope -d -L -1 $sym)
	if [ ! -z "$f" ]; then
		line=$((line-1))
		sed -i "${line}s/^/drm_public /" $f
	fi
done < /tmp/a.txt

Then some corner cases were manually fixed. "a.txt" above contains the
symbols collected from intel/intel-symbol-check. The idea here will be
to switch the default visibility to hidden so we don't export symbols we
shouldn't.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-19 22:46:44 -07:00
Emil Velikov 473e2d2e67 intel: annotate the intel genx helpers as private
They're used internally and never meant to be part of the API.
Add the drm_private notation, which should resolve that.

v2: (Rodrigo) Add missing include.
v3: (Rodrigo) Keep includes grouped per Eric suggestion.

Cc: Eric Engestrom <eric.engestrom@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Fixes: 4e81d4f9c9 ("intel: add generic functions to check PCI ID")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-12 08:47:18 -07:00
Lucas De Marchi c55f1b9b29 intel: get gen once for gen >= 9
We don't need to call IS_GEN() for each gen >= 9: we can rather use the
new intel_is_genx() helper to iterate the pciids array once.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-09-05 16:14:48 -07:00
Lucas De Marchi 584ca8fe53 intel: make gen9 use generic gen macro
The 2 PCI IDs that are used for the command line overrid mechanism
were left defined. The rest can be gone and then we just use the kernel
defines.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-09-05 16:14:41 -07:00
Lucas De Marchi bf9df763d6 intel: make gen10 use generic gen macro
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-09-05 16:14:35 -07:00
Lucas De Marchi 8e7eb3bcfe intel: make gen11 use generic gen macro
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-09-05 16:14:27 -07:00
Lucas De Marchi 4e81d4f9c9 intel: add generic functions to check PCI ID
This will allow platforms to reuse kernel IDs instead of manually
keeping them in sync. In most of the cases we only need to extend
IS_9XX().  Current platforms that fit this requirement can be ported
over to use this macro. Right now it's a nop since it doesn't have any
PCI ID added.

The i915_pciids.h header is in sync with kernel tree on
drm-tip 2018y-08m-20d-21h-41m-11s.

v2: - move to a separate .c so we can have the array in a single
      compilation unit
    - use a single array for all gens
    - add real functions to get or check gen by pciid
    - define our own pci device struct rather than inherit the one
      kernel uses: we can throw away most of the fields

v3: - add comment to keep ids sorted by gen
    - remove misleading comment about all gens

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-09-05 16:14:04 -07:00
Rodrigo Vivi 6e30031788 intel: Add a new CFL PCI ID.
One more CFL ID added to spec.

Align with kernel commit d0e062ebb3a4 ("drm/i915/cfl:
Add a new CFL PCI ID.")

v2: fix commit subject.

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
2018-08-14 16:06:54 -07:00
José Roberto de Souza 7164abebec intel: Introducing Amber Lake platform
Amber Lake uses the same gen graphics as Kaby Lake, including a id
that were previously marked as reserved on Kaby Lake, but that now is
moved to AML page.

So, let's just move it to AML macro that will feed into KBL macro
just to keep it better organized to make easier future code review
but it will be handled as a KBL.

This is a copy of merged i915's
commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform")

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-06-20 16:39:53 -07:00
José Roberto de Souza 591c1d72ab intel: Introducing Whiskey Lake platform
Whiskey Lake uses the same gen graphics as Coffe Lake, including some
ids that were previously marked as reserved on Coffe Lake, but that
now are moved to WHL page.

So, let's just move them to WHL macros that will feed into CFL macro
just to keep it better organized to make easier future code review
but it will be handled as a CFL.

This is a copy of merged i915's
commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform")

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-06-20 16:39:53 -07:00
Paulo Zanoni 1ac3ecde2f intel: add support for ICL 11
Add the PCI IDs and the basic code to enable ICL.  This is the current
PCI ID list in our documentation.

Kernel commit: d55cb4fa2cf0 ("drm/i915/icl: Add the ICL PCI IDs")

v2: Michel provided a fix to IS_9XX that was broken by rebase bot.
v3: Fix double definition of PCI IDs, update IDs according to bspec
    and keep them in the same order and rebase (Lucas)

Cc: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2018-05-01 14:30:25 -07:00
Matt Atwood 50426f3e17 Intel: Add a Kaby Lake PCI ID
Based on kernel commit '672e314b21dc ("drm/i915/kbl: Add KBL GT2 sku")'

v2: name change M -> ULX, add enumeration in KBL ULX
v3: add entry to IS_KABYLAKE

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-04-24 13:05:34 -07:00
Emil Velikov 4dfa458979 Revert "libdrm: intel/Android.mk: Filter libdrm_intel library requirements on x86/x86_64"
This reverts commit ed07718ae7.

The commit added a guard since libpciaccess may be missing on some
setups. As of last commit there are no traces of the project, from
Android POV.

Hence, we can revert this workaround - which caused similar breakage to
the one it's trying to fix. This time in Mesa.

Cc: Rob Herring <rob.herring@linaro.org>
Acked-by: John Stultz <john.stultz@linaro.org>
2018-03-28 17:08:32 +01:00
Tomasz Figa bb0fd5f3b3 intel: Do not use libpciaccess on Android
This patch makes the code not rely anymore on libpciaccess when compiled
for Android to eliminate ioperm() and iopl() syscalls required by that
library. As a side effect, the mappable aperture size is hardcoded to 64
MiB on Android, however nothing seems to rely on this value anyway, as
checked be grepping relevant code in drm_gralloc and Mesa.

Cc: Rob Herring <rob.herring@linaro.org>
Signed-off-by: Tomasz Figa <tfiga@google.com>
[Emil Velikov: rebase against master. add missing __func__, Eric]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: John Stultz <john.stultz@linaro.org>
2018-03-28 17:08:32 +01:00
Eric Engestrom 0926f0af54 meson,configure: include config.h automatically
This will prevent any more missing `#include "config.h"` bug, at the
cost of having to recompile some files that didn't need to be when
changing build options.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-03-20 18:19:26 +00:00
Eric Engestrom 1a44bbae73 meson,configure: always define HAVE_OPEN_MEMSTREAM
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-03-20 14:30:27 +00:00
John Stultz ed07718ae7 libdrm: intel/Android.mk: Filter libdrm_intel library requirements on x86/x86_64
When building AOSP after updating libdrm project to the
freedesktop/master branch, I've seen the following build errors:

external/libdrm/intel/Android.mk: error: libdrm_intel
(SHARED_LIBRARIES android-arm64) missing libpciaccess
(SHARED_LIBRARIES android-arm64) You can set
ALLOW_MISSING_DEPENDENCIES=true in your environment if this is
intentional, but that may defer real problems until later in the
build.

Using ALLOW_MISSING_DEPENDENCIES=true when building allows
things to function properly, but is not ideal.

So basically, while I'm not including the libdrm_intel package
into the build, just the fact that the Android.mk file references
libpciaccess which isn't a repo included in AOSP causes the build
failure.

So it seems we need some sort of conditional filter in the
Android.mk to skip over it if we're not building for intel.

Cc: Chad Versace <chad.versace@linux.intel.com>
Cc: Marissa Wall <marissaw@google.com>
Cc: Sean Paul <seanpaul@google.com>
Cc: Dan Willemsen <dwillemsen@google.com>
Cc: Tomasz Figa <tfiga@google.com>
Cc: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
2018-03-18 23:18:36 -05:00
Eric Engestrom 5236de6cc1 meson: use pkg-config to detect libatomic_ops
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-03-09 17:12:02 +00:00
Rodrigo Vivi 7b12381723 intel/intel_chipset.h: Sync Cannonlake IDs.
Let's sync CNL ids with Spec and kernel.

Sync with kernel commit '3f43031b1693 ("drm/i915/cnl:
Add Cannonlake PCI IDs for another SKU.")' and
commit 'e3890d05b342 ("drm/i915/cnl: Sync PCI ID with Spec.")'

Cc: James Ausmus <james.ausmus@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-03-05 15:13:05 -08:00
Heiko Becker 4f08bfe96d *-symbol-check: Don't hard-code nm executable
Helpful if your nm executable has a prefix based on the
architecture, for example.

Signed-off-by: Heiko Becker <heirecka@exherbo.org>
Cc: Timo Gurr <timo.gurr@gmail.com>
[Eric: v2: rebase and add Meson support]
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-02-23 17:53:08 +00:00
Eric Engestrom 1d7bbf8520 always define HAVE_VALGRIND
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-01-29 15:41:52 +00:00
Dylan Baker 5f7deb5078 Add meson build system
This patch adds a complete meson build system, including tests and
install. It has the necessary hooks to allow it be used as a subproject
for other meson based builds such as mesa.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-and-tested-by: Igor Gnatenko <i.gnatenko.brain@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2018-01-12 09:40:48 -08:00
Anuj Phogat d3cb588315 intel: Add more Coffeelake PCI IDs
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2018-01-11 10:29:02 -08:00
Anuj Phogat 7c71188610 intel: Change a KBL pci id to GT2 from GT1.5
See Mesa commit 9c588ff

Cc: Matt Turner <mattst88@gmail.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-09-21 14:40:41 -07:00
Rodrigo Vivi 68da7812fc intel/intel_chipset: Move IS_9XX below IS_GEN10.
No functional change. Just organizing the code
so it gets clear for future platforms.

Paulo deserves credits becuase he was the one
that just noticed this IS_9XX was in the wrong position
after CNL patches got introduced.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30 14:25:24 -07:00
Paulo Zanoni 3095cc8eab intel: add GEN10 to IS_9XX.
As far as I understand, IS_9XX should return true for it.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30 08:30:48 -07:00
Ben Widawsky 5c490bd685 intel/gen10: Add missed gen10 stuff
This got lost on rebase, I believe

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30 08:30:43 -07:00
Rodrigo Vivi 80201d7067 intel: Add Cannonlake PCI IDs for Y-skus.
By the Spec all CNL Y skus are 2+2, i.e. GT2.

This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")

v2: Add kernel commit id for reference.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
2017-06-30 08:30:28 -07:00
Rodrigo Vivi 6b624bf3c3 intel: Add Cannonlake PCI IDs for U-skus.
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.

This is a copy of merged i915's
commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.")

v2: Remove PCI IDs for SKU not mentioned in spec.
v3: Add kernel commit id for reference.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
2017-06-30 08:30:08 -07:00
Anusha Srivatsa 4c98652cb5 intel: PCI Ids for U SKU in CFL
Add the PCI IDs for U SKU IN CFL by following the spec.

v2: Update IDs

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29 10:51:29 -07:00
Anusha Srivatsa 2b48faf30e intel: PCI Ids for H SKU in CFL
Add the PCI IDs for H SKU IN CFL by following the spec.

v2: Update IDs

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29 10:51:15 -07:00
Anusha Srivatsa 0733f376ae intel: PCI Ids for S SKU in CFL
Add the PCI IDs for S SKU IN CFL by following the spec.

v2: Update IDs.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29 10:50:54 -07:00
Eric Engestrom 3f1df25e0b intel: remove dead code
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
2017-04-10 17:17:12 +01:00
Chris Wilson 19c4cfc549 intel: Add handle to hashtable before freeing along an error path
drm_intel_gem_bo_free() unconditionally attempts to remove the handle
from the hashtable. This goes horribly wrong if we haven't already added
the bo to the hashtable.

Reported-by: Michael Thayer <michael.thayer@oracle.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-03-08 21:03:22 +00:00
Thomas Hindoe Paaboel Andersen 5ee9cb4b4b intel: avoid null pointer dereference
Move the dereference after the null check.
Fixes: 028715ee70 ("intel: Avoid the need for most overflow
                              checks by using a scratch page.")
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-02-28 13:38:09 +00:00
Chris Wilson ec80fd36a7 intel: Move 48b support to bo_gem->kflags
Another boolean that can be set and used along side the other execobject
flags.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-02-11 11:05:42 +00:00
Chris Wilson e0f05b2fad intel: Move is_softpin to obj->kflags
Use obj->kflags to set EXEC_OBJECT_PINNED when the object is softpinned,
and so remember to clear the softpin status when the object is freed
(and reused).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-02-11 11:02:06 +00:00
Dave Airlie 0ad0c12fd3 intel: fix make distcheck
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-01-28 11:13:59 +10:00
Chris Wilson dfd536c60d intel: Export a function to re-enable implicit synchronisation
Implicit synchronisation is the default behaviour of the kernel when
rendering with an execobject. It may be disabled with
drm_intel_gem_bo_disable_implicit_sync(), and then to restore it use
drm_intel_gem_bo_enable_implicit_sync().

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-27 20:25:04 +00:00
Chris Wilson 22cfd04311 intel: Clear execobject flags before preserving object in reuse cache
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-27 20:20:30 +00:00
Chris Wilson c4b00767a7 intel: Support passing of explicit fencing from execbuf
Allow the caller to pass in an fd to an array of fences to control
serialisation of the execbuf in the kernel and on the GPU, and in return
allow creation of a fence fd for signaling the completion (and flushing)
of the batch. When the returned fence is signaled, all writes to the
buffers inside the batch will be complete and coherent from the cpu, or
other consumers. The return fence is a sync_file object and can be
passed to other users (such as atomic modesetting, or other drivers).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-27 20:00:38 +00:00
Chris Wilson 1bd35da961 intel: Allow the client to control implicit synchronisation
The kernel allows implicit synchronisation to be disabled on individual
buffers. Use at your own risk.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-01-27 20:00:38 +00:00
Emil Velikov 03d2e91d00 android: introduce Android.common.mk to reduce boilerplate
... across the makefiles. Currently this isn't much but that will change
shortly.

As an added bonus this fixes all present and future cases where we've
forgotten to strip out the headers from LOCAL_SRC_FILES.

In a couple of cases (the tests) we start setting
LOCAL_EXPORT_C_INCLUDE_DIRS, which shouldn't be an issue.

Cc: Chih-Wei Huang <cwhuang@android-x86.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
2017-01-27 15:48:16 +00:00
Emil Velikov de5b41ef5a android: remove LOCAL_MODULE_TAGS := optional tag
Seems to be the default option since ~2009 with commit 2f31293ba78 "auto
import from //branches/cupcake/...@137197". Fleshed out from a larger
commit in the AOSP repo/fork.

Cc: Dan Willemsen <dwillemsen@google.com>
Cc: Chih-Wei Huang <cwhuang@android-x86.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
2017-01-27 15:47:13 +00:00