a6cc6a778f
add support for setting a framebuffer depth
2007-04-11 17:13:45 +10:00
32f6a58db2
add initial drm_fb framebuffer
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So far I can load fbcon, once I use my miniglx to add a framebuffer.
fbcon doesn't show anything on screen but baby steps and all that.
2007-04-11 16:33:03 +10:00
add7a928ad
comment out unworkable code
2007-04-11 14:43:02 +10:00
3dd5dc5728
only init at driver load
2007-04-11 14:34:43 +10:00
b329f91502
use the baseaddr at least
2007-04-11 14:04:18 +10:00
44be9c9d59
add an fb count + id get to the get resources code path
2007-04-11 13:26:21 +10:00
44a8761302
Merge branch 'modesetting-101' of git+ssh://git.freedesktop.org/git/mesa/drm into origin/modesetting-101
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Conflicts:
linux-core/drm_crtc.c - trivial merge
linux-core/drm_crtc.h - trivial merge
linux-core/intel_display.c - crtc_config -> mode_config
shared-core/i915_dma.c - accommodate new init code in i915_init.c
2007-04-10 10:45:55 -07:00
b59285d738
Move i915 init code to new file, i915_init.c, and create a new high level
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init routine that runs at driver load time.
2007-04-10 10:31:10 -07:00
5130918e25
Add save/restore state for LVDS code, along with a few other LVDS related
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items to i915 private structure.
2007-04-10 09:51:17 -07:00
1e39dc4323
export output name to userspace
2007-04-10 16:25:31 +10:00
40bd6dcd86
set the base address of the CRTC correctly
2007-04-10 15:20:50 +10:00
65f465ed5a
fixup numerous issues with adding framebuffer support
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This still isn't perfect but it fixes a few oopses and cleans up
some of the tabs and bugs in the original fb limit code
2007-04-10 14:49:49 +10:00
b50bda002b
add addfb/rmfb ioctls
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Originally from Jakob, cleaned up by airlied.
2007-04-10 18:44:47 +10:00
b4094864f1
checkpoint commit: implement SetCrtc so modes can in theory be set from user
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This hooks up the userspace mode set it "seems" to work.
2007-04-05 18:01:02 +10:00
7bb112feca
checkpoint commit: added getresources, crtc and output
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This adds the user interfaces from Jakob and hooks them up for 3 ioctls
GetResources, GetCrtc and GetOutput.
I've made the ids for everything fbs, crtcs, outputs and modes go via idr as
per krh's suggestion on irc as it make the code nice and consistent.
2007-04-05 17:06:42 +10:00
5bffbd6e27
initial userspace interface to get modes
2007-04-05 13:34:50 +10:00
52f9028c84
Initial import of modesetting for intel driver in DRM
2007-04-05 11:21:06 +10:00
139e4bbc73
Make sure we ack irqs before we read a breadcrumb so that
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breadcrumb updates that occur _AFTER_ we've read the breadcrumb really
generates a new IRQ.
2007-04-03 10:29:15 +02:00
5395a92d40
r300: Synchronize the register header file again.
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It's a good idea to keep these synchronized; even though the DRM doesn't use all
the defines, maintaining two different copies is prone to errors when the diff
gets bigger.
2007-04-02 19:45:10 +00:00
cbbdbd5e65
nouveau: fix usage of PGRAPH_CTX_CONTROL on nv20+
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http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=17985f07d68322519919a7f629a6d2d9bf3916ed could have broken some nvxx_graph code : it rename NV03_PGRAPH_CTX_CONTROL to NV10_PGRAPH_CTX_CONTROL, but forgot to update it in nvxx_graph file.
Also when migrating init stuff in http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=674cefd4fe4b537a20a10edcb4ec5df55facca8e , NV04_PGRAPH_CTX_CONTROL is used everywhere but the old ddx code use NV_PGRAPH_CTX_CONTROL_NV04 or NV_PGRAPH_CTX_CONTROL.
2007-04-01 14:31:41 +02:00
25cedcf76f
nouveau : nv10 ctx switch fix
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restoring NV10_PGRAPH_CTX_SWITCH1 now works
2007-04-01 14:21:29 +02:00
223061e084
nouveau : set the correct PGRAPH_CTX_CONTROL register
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"5a072f32 (Stephane Marchesin 2007-02-03 04:57:06 +0100" broke nv10 ctx switch by setting wrong PGRAPH_CTX_CONTROL reg
2007-04-01 00:44:11 +02:00
ddb1715e06
Merge branch 'crestline-qa', adding support for the 965GM chipset.
2007-03-30 13:11:39 -07:00
bdabc8f998
nouveau: fix nv04 context switches.
2007-03-29 00:54:18 +02:00
81b811da37
drm/i915: set the bo up at firstopen time not after DMA init
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This is required to use TTM to allocate the ring buffer.
2007-03-27 18:01:31 +10:00
406a894e52
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-27 12:53:13 +08:00
674cefd4fe
nouveau: move card initialisation into the drm
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The PGRAPH init for the various cards will need cleaning up at some point,
a lot of the values written there are per-context state left over from the
all the hardcoding done in the ddx.
It's possible some cards get broken by this commit, let me know.
Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 20:59:37 +10:00
e7cd5a1e2d
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-23 17:00:41 +08:00
4988fa4886
nouveau: rework nouveau_fifo_alloc() so the drm can create internal FIFOs
2007-03-23 15:25:37 +11:00
2bb9de96d5
nouveau: remove unused cruft
2007-03-23 13:45:29 +11:00
0467ad4118
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-21 17:00:43 +08:00
e22225416a
nouveau: support multiple channels per client (breaks drm interface)
2007-03-21 17:57:47 +11:00
8398b99d8d
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-19 17:00:31 +08:00
26aba875e1
more whitespace issues
2007-03-19 08:56:24 +11:00
2463b03cb4
whitespace cleanup pending a kernel merge
2007-03-19 08:23:43 +11:00
df73975980
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-14 17:00:27 +08:00
93f66af76a
r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; not
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enough information is known about them to be sure as to what the values mean.
2007-03-13 14:48:01 +00:00
80d0018bc0
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-13 17:00:31 +08:00
a90c2854a7
Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.
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Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these
values are really unknown; ideally more reverse engineering should be done to
determine what these values mean and when they should be set.
2007-03-13 06:25:04 +00:00
90f8c691a5
nouveau: make sure cmdbuf object gets destroyed
2007-03-13 14:55:54 +11:00
1775202cf9
nouveau: associate all created objects with a channel + cleanups
2007-03-13 14:55:54 +11:00
7e2bbe2954
nouveau: s/fifo/channel/
2007-03-13 14:55:54 +11:00
462a6ea4ca
Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to either
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R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values.
2007-03-13 01:19:56 +00:00
5667396e05
Guess another unknown register used for R300 pacification.
2007-03-13 00:50:05 +00:00
ab75d50d6c
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-12 09:03:40 +08:00
0cd5c650d1
nouveau: PUT,GET, not 2xPUT
2007-03-11 14:02:40 +01:00
b369724077
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-07 16:01:50 -05:00
6ffe94f008
Add via CX700.
2007-03-07 09:19:57 +01:00
0a85c9fa02
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-05 09:01:45 -05:00
188a93c9df
radeon: make PCI GART aperture size variable, but making table size variable
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This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0
2007-03-04 19:10:46 +11:00
David Airlie
Dave Airlie
Jesse Barnes
Jakob Bornecrantz
Dave Airlie
Thomas Hellstrom
Oliver McFadden
Matthieu Castet
Eric Anholt
Stephane Marchesin
Nian Wu
Ben Skeggs
Patrice Mandin