36e11dd380
r500: fragment program upload is also used to upload constants.
...
Limit frag address to 8 bits
2008-03-21 16:59:52 +10:00
3add949403
initial r500 RS and FP register and upload code
2008-03-17 11:08:03 +10:00
a90510966e
radeon: refactor out the fb/agp location read/write.
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Add a new get param to get the fb location into userspace. Mesa currently
hits MMIO to do this, but this isn't always possible.
2007-11-18 19:25:31 +10:00
7f6bf84c23
drm: remove lots of spurious whitespace.
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Kernel "cleanfile" script run.
2007-11-05 12:42:22 +10:00
b95ac8b7b3
drm: detypedef drm.h and fixup all problems
2007-07-16 11:22:15 +10:00
4e9d215bdf
radeon: add support for vblank on crtc2
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This add support for CRTC2 vblank on radeon similiar to the i915 support
2007-06-03 16:28:21 +10:00
188a93c9df
radeon: make PCI GART aperture size variable, but making table size variable
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This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0
2007-03-04 19:10:46 +11:00
f4e6e4499c
Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, and new
...
packet type for making it possible to address whole tcl vector space
and have a larger count)
2006-05-24 18:36:24 +00:00
b3fdf9bb7a
Add general-purpose packet for manipulating scratch registers (r300)
2006-03-06 20:08:50 +00:00
9fad101da9
add benh's memory management patch
2006-02-18 03:04:30 +00:00
4791dc8856
major realigment of DRM CVS with kernel code, makes integration much easier
2006-02-18 02:53:36 +00:00
780e90e4a2
add radeon card type get param so userspace can avoid walking PCI
2005-12-29 00:17:51 +00:00
6ff57e2d7c
fix pci overriding from userspace
2005-09-30 06:35:09 +00:00
5565a00916
Add GART in FB support for ati pcigart, and PCIE support for r300
2005-09-11 08:51:23 +00:00
53c8037786
Add support for GL_ATI_fragment_shader, new packets R200_EMIT_PP_AFS_0/1,
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R200_EMIT_PP_TXCTLALL_0-5 (replaces R200_EMIT_PP_TXFILTER_0-5, 2 more
regs) and R200_EMIT_ATF_TFACTOR (replaces R200_EMIT_TFACTOR_0 (8 consts
instead of 6)
2005-09-09 22:35:49 +00:00
bb9502ab01
Mark some radeon init variables deprecated. These used to be passed in but
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the driver already knew their correct value. For example the physical
address of the framebuffer and registers.
2005-08-04 13:59:48 +00:00
ab59dd285c
Add latest r300 support from r300.sf.net CVS. Patch submitted by volodya,
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with BSD fix from jkim and the r300_reg.h license from Nicolai Haehnle.
Big thanks to everyone involved!
2005-07-20 21:17:47 +00:00
34563921dd
add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear filtering on
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r200
2005-03-15 22:12:30 +00:00
732cdc5cef
add support for texture micro tiling on radeon/r200. Add support for r100
...
cube maps (since it also requires a version bump) at the same time.
2005-02-10 19:22:43 +00:00
43c3223de6
(Stephane Marchesin,me) Add radeon framebuffer tiling support to radeon
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drm. Add new ioctls to manage surfaces which cover the tiled areas
2005-01-26 17:48:59 +00:00
c4a87c6883
(Stephane Marchesin, me) add hyperz support to radeon drm. Only fast z
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clear and z buffer compression are working correctly, hierarchical-z is
not.
2004-12-08 16:43:00 +00:00
3f02a79351
Vladimir requested support so we can at least load r300 microcode for
...
helping
2D operations.
Ups radeon to version 1.12.0, Vladimir, you might want to add any extra
pciids...
Approved-by: Dave Airlie <airlied@linux.ie>
2004-10-10 05:52:19 +00:00
9f9a8f1382
Lindent of core build. Drivers checked for no binary diffs. A few files
...
weren't Lindent's because their comments didn't convert very well. A
bunch of other minor clean up with no code implact included.
2004-09-30 21:12:10 +00:00
93e8c201af
preparation patch for radeon permanent mapping registers/framebuffer makes
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dev_priv live always, and add AGP detection in kernel patch:
radeon-pre-2.patch From: Jon Smirl
2004-08-17 11:24:50 +00:00
02df04d71d
sync up with current 2.6 kernel bk tree - mostly __user annotations
2004-07-25 08:47:38 +00:00
aa142ff1b5
add R200_EMIT_RB3D_BLENDCOLOR state packet to support GL_EXT_blend_color,
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GL_EXT_blend_func_separate and GL_EXT_blend_equation_separate on r200
2004-05-18 23:03:22 +00:00
3306abbde7
white space changes to align with kernel
2004-04-10 13:52:43 +00:00
24115068e4
Fixes need to clean up the mess I made with the mesa merge. This code
...
allows the mesa drivers to use a single definition of the DRM
sarea/IOCTLS located in the drm driver directory. Adjustments were made
to the 2D drivers to not include these changes. Changes to the mesa
copy of DRM were copied to the DRI copy. XFree86 bug: Reported by:
Submitted by: Reviewed by: Obtained from:
2004-03-12 21:22:52 +00:00
2655ccddf4
Memory layout transition:
...
the 2D driver initializes MC_FB_LOCATION and related registers sanely
the DRM deduces the layout from these registers
clients use the new SETPARAM ioctl to tell the DRM where they think the
framebuffer is located in the card's address space
the DRM uses all this information to check client state and fix it up if
necessary
This is a prerequisite for things like direct rendering with IGP chips and
video capturing.
2003-11-04 00:46:05 +00:00
062751ac47
Remove artificial PCI GART limitations, rename AGP to GART where
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appropriate
2003-08-26 15:44:01 +00:00
c99acb597f
Added some information as to when (which DRM version) various queries were
...
added.
2003-08-08 21:06:44 +00:00
0b01c70d59
Texture rectangle support for r100
2003-06-10 18:54:17 +00:00
c0efa1a777
DRM part of Radeon DRI suspend/resume support (Charl Botha).
2003-05-20 22:43:39 +00:00
285b1cdc39
Merged texmem-0-0-1
2003-04-30 01:51:00 +00:00
13211ad82c
add more get_param queries for embedded project
2003-04-22 09:49:14 +00:00
cfa778af9c
Merge from bsd-4-0-0-branch.
2003-02-21 23:23:09 +00:00
f3751850c8
Fix size of VERTEX2 ioctl struct (Egbert Eich)
2003-02-03 14:30:32 +00:00
344c7f6b41
updated e-mail addresses for Keith, Alan and Jens
2002-10-29 20:29:05 +00:00
5e1b8ed88a
preserve CRTC{,2}_OFFSET_CNTL in 2D driver to avoid bad effects when
...
pageflipping after a mode switch
take current page into account in AdjustFrame(); writing the CRTC offset
via the CP was probably a bad idea as this can happen asynchronously,
reverted
take frame offset into account when flipping pages
handle CRTC2 as well for pageflipping (untested)
preserve GEN_INT_CNTL on mode switches to prevent interrupts from getting
disabled
2002-10-29 13:49:26 +00:00
ff25e7016c
merge from mesa-4-1-branch to get cube-map registers. bumped version to 1.7
2002-10-28 19:05:40 +00:00
f40674ea9f
change RADEON_PARAM_IRQ_ACTIVE to RADEON_PARAM_IRQ_NR
2002-09-25 19:48:51 +00:00
f1c8fe9557
merged r200-0-2-branch to trunk
2002-09-23 17:26:43 +00:00
48cc350e21
merged r200-0-1-branch
2002-08-26 22:16:18 +00:00
fd86ac9561
Don't read scratch registers directly, obtain the values via the GET_PARAM
...
ioctl. The DRM reads them from memory addresses the chip writes to on
updates. Fall back to reading the registers directly with an old DRM.
(Tim Smith, cleanups by myself)
2002-07-11 20:31:12 +00:00
74ef13fd00
merged bsd-3-0-0-branch
2002-07-05 08:31:11 +00:00
Dave Airlie
Dave Airlie
Roland Scheidegger
Aapo Tahkola
Jon Smirl
Eric Anholt
Michel Daenzer
Ian Romanick
Keith Whitwell
David Dawes
Jens Owen
Brian Paul
Alan Hourihane