Commit Graph

106 Commits (315fef7ee44f9ca565f158a6a84fd29b34e69fd8)

Author SHA1 Message Date
Ben Skeggs 1ccccbd4ce nouveau: redo channel idle detection
Will hopefully work a bit better than previous code, which depended on
knowing the channel's most recent PUT value.  Some chips always return
0 on reading these regs, and currently userspace is the only other entity
which knows the value.
2008-03-07 15:18:34 +11:00
Ben Skeggs cd924de029 nouveau: don't touch NV_USER regs on channel destroy.
Not only was this entirely pointless, it actually causes my NV30GL to
die randomly when channels are destroyed.
2008-03-07 15:18:34 +11:00
Maarten Maathuis 0d32015974 nouveau: Remove some random (french) comment. 2008-02-22 19:28:54 +01:00
Ben Skeggs 9a7e45858d nv40: some more nv67 changes
With some luck the drm-side will be OK now for this chipset.
2008-01-30 11:50:17 +11:00
Ben Skeggs 2d7eb4434f nouveau: Also wait until CACHE1 gets emptied. 2007-11-14 05:36:20 +11:00
Ben Skeggs 7e4bb6099a Revert "nouveau: stub superioctl"
This reverts commit 2370ded79b.

Err.. didn't mean for that to slip in :)
2007-11-14 05:11:11 +11:00
Ben Skeggs eb5487b9ca Merge branch 'fifo-cleanup' into upstream-master 2007-11-14 05:09:07 +11:00
Ben Skeggs 7c1e59fb0c nouveau: Attempt to wait for channel idle before we destroy it. 2007-11-14 04:26:49 +11:00
Ben Skeggs 53ab6026cf nouveau: Use "new" NV40 USER control regs.
Probably entirely pointless, but a simple change in any case.
2007-11-14 04:15:13 +11:00
Ben Skeggs 7246a33dd1 nouveau: store user control reg offsets in channel struct 2007-11-14 04:09:53 +11:00
Ben Skeggs d0904f0f2b nouveau: funcs to determine active channel on PFIFO. 2007-11-14 03:27:37 +11:00
Ben Skeggs 2370ded79b nouveau: stub superioctl 2007-11-14 03:00:25 +11:00
Dave Airlie 7f6bf84c23 drm: remove lots of spurious whitespace.
Kernel "cleanfile" script run.
2007-11-05 12:42:22 +10:00
Matthieu Castet f8f31f0457 nouveau : stop the fifo of the channel we are deleting 2007-09-29 23:07:29 +02:00
Stephane Marchesin 69b11f44f0 nouveau: give nv03 the last cut. 2007-08-31 01:40:00 +02:00
Ben Skeggs 216f1b0573 nouveau: Poke 0x2230 on NV47 also.
Makes 0x2220 work the same way as on NV40.
2007-08-21 02:18:27 +10:00
Ben Skeggs a46104674f nouveau/nv50: demagic instmem setup. 2007-08-10 14:22:50 +10:00
Ben Skeggs 05633ca370 nouveau: Always allocate drm's push buffer in VRAM
Fixes #11868
2007-08-08 16:37:55 +10:00
Ben Skeggs 4ad487190d nouveau: enable/disable engine-specific interrupts in _init()/_takedown()
All interrupts are still masked by PMC until init is finished.
2007-08-08 10:49:05 +10:00
Ben Skeggs 7a0a812ea4 nouveau: Remove PGRAPH_SURFACE hack, it wont work now anyway.
Need to find another way of doing this, ideally someone'd hunt down which
object/method controls it!  The Xv blit adaptor is likely now broken on
cards that have pNv->WaitVSyncPossible enabled.
2007-08-06 22:09:15 +10:00
Ben Skeggs cf04641bc6 nouveau: Give DRM its own gpu channel
If your card doesn't have working context switching, it is now broken.
2007-08-06 22:05:31 +10:00
Ben Skeggs 97770db720 nouveau: Various internal and external API changes
1. DRM_NOUVEAU_GPUOBJ_FREE
	Used to free GPU objects.  The obvious usage case is for Gr objects,
	but notifiers can also be destroyed in the same way.

	GPU objects gain a destructor method and private data fields with
	this change, so other specialised cases (like notifiers) can be
	implemented on top of gpuobjs.

2. DRM_NOUVEAU_CHANNEL_FREE

3. DRM_NOUVEAU_CARD_INIT
	Ideally we'd do init during module load, but this isn't currently
	possible.  Doing init during firstopen() is bad as X has a love of
	opening/closing the DRM many times during startup.  Once the
	modesetting-101 branch is merged this can go away.

	IRQs are enabled in nouveau_card_init() now, rather than having the
	X server call drmCtlInstHandler().  We'll need this for when we give
	the kernel module its own channel.

4. DRM_NOUVEAU_GETPARAM
	Add CHIPSET_ID value, which will return the chipset id derived
	from NV_PMC_BOOT_0.

4. Use list_* in a few places, rather than home-brewed stuff.
2007-08-06 21:45:18 +10:00
Ben Skeggs beaa0c9a28 nouveau: Pass channel struct around instead of channel id. 2007-08-06 03:40:43 +10:00
Eric Anholt 5b38e13416 Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE.
The data is now in kernel space, copied in/out as appropriate according to the
This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal
with those failures.  This also means that XFree86 4.2.0 support for i810 DRM
is lost.
2007-07-20 18:16:42 -07:00
Eric Anholt c1119b1b09 Replace filp in ioctl arguments with drm_file *file_priv.
As a fallout, replace filp storage with file_priv storage for "unique
identifier of a client" all over the DRM.  There is a 1:1 mapping, so this
should be a noop.  This could be a minor performance improvement, as everything
on Linux dereferenced filp to get file_priv anyway, while only the mmap ioctls
went the other direction.
2007-07-20 13:39:45 -07:00
Eric Anholt e39286eb5e Remove DRM_ERR OS macro.
This was used to make all ioctl handlers return -errno on linux and errno on
*BSD.  Instead, just return -errno in shared code, and flip sign on return from
shared code to *BSD code.
2007-07-20 12:53:52 -07:00
Ben Skeggs ec67c2def9 nouveau: G8x PCIEGART
Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART
support for G8X using the current mm has been hacked on top of it.
2007-07-17 13:51:14 +10:00
Dave Airlie 21ee6fbfb8 drm: remove drmP.h internal typedefs 2007-07-16 12:32:51 +10:00
Patrice Mandin bc7d6c76fa nouveau: nv10 and nv11/15 are different 2007-07-14 18:32:11 +02:00
Ben Skeggs 0029713451 nouveau: nuke internal typedefs, and drm_device_t use. 2007-07-13 15:09:31 +10:00
Ben Skeggs 750371cb6e nouveau: separate region_offset into map_handle and offset. 2007-07-12 10:46:57 +10:00
Arthur Huillet 5fbdf9da8b fixed object creation code to not Oops on 64bits, worked around memalloc not working on 64bit for PCIGART 2007-07-12 02:35:39 +02:00
Arthur Huillet d26ae22c2b fixed bug that prevented PCIE cards from actually using PCIGART - NV50 will probably still have a problem 2007-07-11 14:56:27 +02:00
Ben Skeggs 13e1377044 nouveau: Some checks on userspace object handles. 2007-07-11 12:39:30 +10:00
Arthur Huillet 694e1c5c3f Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel. 2007-07-11 02:35:10 +02:00
Ben Skeggs 023f7d9c00 nouveau: Allocate mappable VRAM for notifiers.. 2007-07-09 23:58:00 +10:00
Ben Skeggs c806bba466 nouveau/nv50: Initial channel/object support
Should be OK on G84 for a single channel, multiple channels *almost* work.

Untested on G80.
2007-07-09 16:16:44 +10:00
Ben Skeggs 163f852612 nouveau: rewrite gpu object code
Allows multiple references to a single object, needed to support PCI(E)GART
scatter-gather DMA objects which would quickly fill PRAMIN if each channel
had its own.

Handle per-channel private instmem areas.  This is needed to support NV50,
but might be something we want to do on earlier chipsets at some point?

Everything that touches PRAMIN is a GPU object.
2007-07-09 16:16:44 +10:00
Ben Skeggs 1c32fecd6d nouveau: Hack around possible Xv blit adaptor breakage 2007-06-28 21:01:17 +10:00
Ben Skeggs 695599f18d nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)
For various reasons, this ioctl was a bad idea.

At channel creation we now automatically create DMA objects covering
available VRAM and GART memory, where the client used to do this themselves.

However, there is still a need to be able to create DMA objects pointing at
specific areas of memory (ie. notifiers).  Each channel is now allocated a
small amount of memory from which a client can suballocate things (such as
notifiers), and have a DMA object created which covers the suballocated area.
The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-28 03:26:43 +10:00
Ben Skeggs 9f617522d9 nouveau: NV49/NV4B PGRAPH setup from jb17bsome and stephan_2303 2007-06-25 01:57:57 +10:00
Ben Skeggs 3dfc13e2da nouveau: kill some dead code 2007-06-24 19:00:44 +10:00
Ben Skeggs 5f05cd7086 nouveau: NV04/NV10/NV20 PGRAPH engtab functions
NV04/NV10 load_context()/save_context() are stubs.  I don't know enough about
how they work to implement them sanely.  The "old" context_switch() code
remains hooked up, so it shouldn't break anything.

NV20 will probably break if load_context() works.  No inital context values
are filled in, so when the first channel is created PGRAPH will probably end
up having its state zeroed.  Some setup from nv20_graph_init() will probably
need to be moved to the per-channel context setup.
2007-06-24 19:00:26 +10:00
Ben Skeggs 5d55b0655c nouveau: NV3X PGRAPH engtab functions 2007-06-24 18:58:38 +10:00
Ben Skeggs 341bc78207 nouveau: NV1X/2X/3X PFIFO engtab functions
Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC
entry size.
2007-06-24 18:58:14 +10:00
Ben Skeggs 05d86d950a nouveau: NV04 PFIFO engtab functions 2007-06-24 18:57:09 +10:00
Ben Skeggs acb710d1a5 nouveau: NV4X PGRAPH engtab functions 2007-06-24 18:56:40 +10:00
Ben Skeggs f2e64d5276 nouveau: NV4X PFIFO engtab functions 2007-06-24 18:56:01 +10:00
Ben Skeggs 0afb3b518e nouveau: split PFIFO/PGRAPH context creation 2007-06-24 18:55:23 +10:00
Ben Skeggs 9dbf322d26 nouveau: (mostly) hook up put_base again 2007-06-24 18:55:06 +10:00