Commit Graph

85 Commits (35d1b13b4a574faf3a95bf3b7cdd14897ef07f67)

Author SHA1 Message Date
Ben Skeggs 9a7e45858d nv40: some more nv67 changes
With some luck the drm-side will be OK now for this chipset.
2008-01-30 11:50:17 +11:00
Stephane Marchesin 616cef5ec8 nouveau: don't forget NV80. 2008-01-21 21:11:47 +01:00
Stephane Marchesin 641c9a2ecc nouveau: new card family for old card designs. 2008-01-21 21:01:28 +01:00
Ben Skeggs 3d248cd7e4 nv50: hook up timer funcs... 2008-01-07 17:23:31 +11:00
Stephane Marchesin cd19dcef4f Nouveau: ppc oops. 2008-01-07 06:11:33 +01:00
Stephane Marchesin de522ae742 Nouveau: move PPC bios copy to firstopen. 2008-01-07 05:54:37 +01:00
Maarten Maathuis 887b920a7f nouveau: Properly identify NV40 and NV44 generation. 2007-11-30 22:50:34 +01:00
Stephane Marchesin 307fc3c92c nouveau: also mention the number of succcessfully copied bios bytes. 2007-11-16 15:02:47 +01:00
Stephane Marchesin baf5d20297 nouveau: be verbose about PPC bios for now. 2007-11-15 20:42:38 +01:00
Stephane Marchesin 3c998d8fcb nouveau: use get_property instead of of_get_property on pre-2.6.22 kernels. 2007-11-15 16:00:54 +01:00
Stephane Marchesin 2cf7ad0d9b nouveau: Copy the PPC bios to RAMIN on init, that lets us do proper output detection in user space. 2007-11-15 03:44:01 +01:00
Ben Skeggs 7e4bb6099a Revert "nouveau: stub superioctl"
This reverts commit 2370ded79b.

Err.. didn't mean for that to slip in :)
2007-11-14 05:11:11 +11:00
Ben Skeggs eb5487b9ca Merge branch 'fifo-cleanup' into upstream-master 2007-11-14 05:09:07 +11:00
Ben Skeggs d0904f0f2b nouveau: funcs to determine active channel on PFIFO. 2007-11-14 03:27:37 +11:00
Ben Skeggs 2370ded79b nouveau: stub superioctl 2007-11-14 03:00:25 +11:00
Dave Airlie 7f6bf84c23 drm: remove lots of spurious whitespace.
Kernel "cleanfile" script run.
2007-11-05 12:42:22 +10:00
Ben Skeggs 9a999e57af nouveau: crappy ttm mm init, disabled for now. 2007-11-05 01:20:32 +11:00
Stephane Marchesin cc745fcc3a nouveau: don't touch PMC_BOOT_1 on x86, it seems to be undefined on some early cards. 2007-10-28 01:59:39 +02:00
Stephane Marchesin 30353c8efc nouveau: PPC fixes. These regs are very touchy. 2007-10-14 23:08:36 +02:00
Maarten Maathuis d912709a63 nouveau: PMC_BOOT_1 was not mapped. 2007-10-10 16:41:21 +02:00
Stephane Marchesin 9b294bbe0e nouveau: try to fix big endian. 2007-10-10 01:12:20 +02:00
Maarten Maathuis 20928a2f2b nouveau: A char is signed, so it may overflow for >NV50. 2007-10-07 19:01:58 +02:00
Maarten Maathuis d351601899 nouveau: Remove excess device classes. 2007-10-04 09:46:16 +02:00
Maarten Maathuis b510517d59 nouveau: Switch over to using PMC_BOOT_0 for card detection. 2007-10-04 09:31:46 +02:00
Maarten Maathuis 69fcfb413e nouveau: Fix dereferencing a NULL pointer when erroring out during initialization. 2007-10-01 22:21:23 +02:00
Pekka Paalanen 205403aea8 nouveau: nv30 graph function renames, removed nv20_graph.c
All nv30 functions in nv30_graph.c that can be used on nv20 are renamed
as accordingly. nv20 specific parts from nv20_graph.c are moved into
nv30_graph.c.
2007-09-30 22:16:01 +03:00
Pekka Paalanen dc592c8b7b nouveau: Make nv20 use the nv30 PGRAPH ctx functions. 2007-09-30 22:16:01 +03:00
Stephane Marchesin 69b11f44f0 nouveau: give nv03 the last cut. 2007-08-31 01:40:00 +02:00
Ben Skeggs 02c4e0e757 nouveau/nv40: Fix channel scheduling.
Ensure NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLE gets set, otherwise channels
will appear to "freeze" in some circumstances.
2007-08-15 01:04:41 +10:00
Ben Skeggs 39907f613b nouveau: Allow creation of gpuobjs before any other init has taken place. 2007-08-10 13:53:10 +10:00
Matthieu Castet a4759b8513 nouveau : fix enable irq (in the previous code all irq were masked by engine
init after irq_postinstall)
2007-08-07 23:09:44 +02:00
Ben Skeggs 66f5232d93 nouveau: Init global gpuobj list early, unbreaks sgdma code. 2007-08-07 01:52:49 +10:00
Ben Skeggs cf04641bc6 nouveau: Give DRM its own gpu channel
If your card doesn't have working context switching, it is now broken.
2007-08-06 22:05:31 +10:00
Ben Skeggs 97770db720 nouveau: Various internal and external API changes
1. DRM_NOUVEAU_GPUOBJ_FREE
	Used to free GPU objects.  The obvious usage case is for Gr objects,
	but notifiers can also be destroyed in the same way.

	GPU objects gain a destructor method and private data fields with
	this change, so other specialised cases (like notifiers) can be
	implemented on top of gpuobjs.

2. DRM_NOUVEAU_CHANNEL_FREE

3. DRM_NOUVEAU_CARD_INIT
	Ideally we'd do init during module load, but this isn't currently
	possible.  Doing init during firstopen() is bad as X has a love of
	opening/closing the DRM many times during startup.  Once the
	modesetting-101 branch is merged this can go away.

	IRQs are enabled in nouveau_card_init() now, rather than having the
	X server call drmCtlInstHandler().  We'll need this for when we give
	the kernel module its own channel.

4. DRM_NOUVEAU_GETPARAM
	Add CHIPSET_ID value, which will return the chipset id derived
	from NV_PMC_BOOT_0.

4. Use list_* in a few places, rather than home-brewed stuff.
2007-08-06 21:45:18 +10:00
Ben Skeggs beaa0c9a28 nouveau: Pass channel struct around instead of channel id. 2007-08-06 03:40:43 +10:00
Eric Anholt 5b38e13416 Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE.
The data is now in kernel space, copied in/out as appropriate according to the
This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal
with those failures.  This also means that XFree86 4.2.0 support for i810 DRM
is lost.
2007-07-20 18:16:42 -07:00
Eric Anholt c1119b1b09 Replace filp in ioctl arguments with drm_file *file_priv.
As a fallout, replace filp storage with file_priv storage for "unique
identifier of a client" all over the DRM.  There is a 1:1 mapping, so this
should be a noop.  This could be a minor performance improvement, as everything
on Linux dereferenced filp to get file_priv anyway, while only the mmap ioctls
went the other direction.
2007-07-20 13:39:45 -07:00
Eric Anholt e39286eb5e Remove DRM_ERR OS macro.
This was used to make all ioctl handlers return -errno on linux and errno on
*BSD.  Instead, just return -errno in shared code, and flip sign on return from
shared code to *BSD code.
2007-07-20 12:53:52 -07:00
Pekka Paalanen af4cfa624a nouveau: Make nouveau_wait_for_idle() read PTIMER.
Following my nv28 kmmio dumps, nouveau_wait_for_idle() is modified to
read PTIMER and NV03_PMC_ENABLE. Also a timeout based on PTIMER value is
added, so wait_for_idle() cannot stall indefinitely (unless PTIMER is
halted). The timeout was selected as 1 giga-ticks, which for me is 1s.
2007-07-18 14:23:41 +03:00
Pekka Paalanen 696bee093f nouveau: Add read() method to Engine.timer.
This is not called from anywhere, yet.
2007-07-18 14:12:26 +03:00
Ben Skeggs ec67c2def9 nouveau: G8x PCIEGART
Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART
support for G8X using the current mm has been hacked on top of it.
2007-07-17 13:51:14 +10:00
Ben Skeggs 0029713451 nouveau: nuke internal typedefs, and drm_device_t use. 2007-07-13 15:09:31 +10:00
Arthur Huillet d26ae22c2b fixed bug that prevented PCIE cards from actually using PCIGART - NV50 will probably still have a problem 2007-07-11 14:56:27 +02:00
Arthur Huillet 694e1c5c3f Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel. 2007-07-11 02:35:10 +02:00
Ben Skeggs 3c58195ccd nouveau: Avoid oops
Turns out lastclose() gets called even if firstopen() has never been...
2007-07-09 16:16:44 +10:00
Ben Skeggs c806bba466 nouveau/nv50: Initial channel/object support
Should be OK on G84 for a single channel, multiple channels *almost* work.

Untested on G80.
2007-07-09 16:16:44 +10:00
Ben Skeggs 163f852612 nouveau: rewrite gpu object code
Allows multiple references to a single object, needed to support PCI(E)GART
scatter-gather DMA objects which would quickly fill PRAMIN if each channel
had its own.

Handle per-channel private instmem areas.  This is needed to support NV50,
but might be something we want to do on earlier chipsets at some point?

Everything that touches PRAMIN is a GPU object.
2007-07-09 16:16:44 +10:00
Ben Skeggs 2dd85772aa nouveau/nv10: Fix earlier NV1x chips
Can't use nv04 code for them, since an extra field was inserted into
RAMFC after DMA_PUT/GET.
2007-06-28 04:23:17 +10:00
Ben Skeggs 18a6d1c9c3 nouveau: simplify PRAMIN access 2007-06-28 03:26:44 +10:00
Ben Skeggs ce0d528d3c nouveau/nv50: skeletal backend 2007-06-28 03:26:43 +10:00