Commit Graph

2724 Commits (3fc3fc082adfa9a7dfe45ea8fb7a9fb6e7019ff6)

Author SHA1 Message Date
Eric Anholt 3d3a96ad4e Merge branch 'origin' into bo-set-pin 2007-09-19 15:55:58 -07:00
Michel Dänzer e349b58b4a i915: Reinstate check that drawable has valid information in i915_vblank_swap. 2007-09-18 21:06:55 +01:00
Michel Dänzer 78d111fa96 i915: Fix scheduled buffer swaps.
One instance of unlocking a spinlock was converted incorrectly when this code
was fixed to build on BSD.
2007-09-18 21:06:55 +01:00
Ian Romanick a3881ad2fe Add ioc32 compat layer for XGI DRM. 2007-09-18 11:03:49 -07:00
Ian Romanick e7d4a26913 Fix ioc32 compat layer
Previously any ioctls that weren't explicitly listed in the compat ioctl
table would fail with ENOTTY.  If the incoming ioctl number is outside the
range of the table, assume that it Just Works, and pass it off to drm_ioctl.
This make the fence related ioctls work on 64-bit PowerPC.
2007-09-18 11:03:08 -07:00
Brian 41345b95a2 Added bool typedef added in kernel 2.6.19
This allows the xgi code to compile with older kernels.
2007-09-12 12:05:15 -06:00
Brian c453135789 Added idr_replace() function which was apparently added in Linux 2.6.18
Someone should probably double-check my work here since this is the
first time I've touched drm_compat.[ch]
2007-09-12 11:49:51 -06:00
Jesse Barnes 852232fb80 Remove plane->pipe mapping from SAREA private after all
We can figure out which pipe a given plane is mapped to by looking at the
display control registers instead of tracking it in a new SAREA private field.
If this becomes a performance problem, we could move to an ioctl based solution
by adding a new parameter for the DDX to set (defaulting to the old behavior if
the param was never set of course).
2007-09-12 08:55:33 -07:00
Jesse Barnes 7fdf98051a Merge branch 'master' of ssh://git.freedesktop.org/git/mesa/drm 2007-09-11 03:50:17 -07:00
Jesse Barnes 3cb8acd5ab Disambiguate planes & pipes for swap operations
This mod makes the SAREA track plane to pipe mappings and corrects the name of
the plane info variables (they were mislabeled as pipe info since until now all
code assumed a direct mapping between planes and pipes).

It also updates the flip ioctl argument to take a set of planes rather than
pipes, since planes are flipped while pipes generate vblank events.
2007-09-11 03:48:46 -07:00
Patrice Mandin 0bd8752a0c nouveau: nv10: add combiner registers 2007-09-10 18:53:48 +02:00
Matthieu Castet 00bb534a54 nouveau : nv10 fix NV10_PGRAPH_CTX_USER save/load 2007-09-09 15:49:33 +02:00
Matthieu Castet b2ee72f440 nouveau : nv10 pipe ctx switch load/save.
This fix some issues with more than one 3D fifo, but there still some "corruption" sometimes
2007-09-09 12:13:00 +02:00
Maarten Maathuis f19d80b046 nouveau: Add Quadro NVS 140 pciid 2007-09-08 22:19:00 +02:00
Ben Skeggs 06bb072595 nouveau: Use nv41 ctxprog/vals on nv42. 2007-09-07 20:07:13 +10:00
Ian Romanick 54c96cbc46 Merge branch 'xgi-0-0-2' 2007-09-06 15:37:52 -07:00
Ian Romanick c597bd57ee Bump version to 1.0.0. 2007-09-06 15:20:52 -07:00
Stephane Marchesin edf5a86a26 nouveau: fix some nv04 graph switching. 2007-09-06 02:47:06 +02:00
Stephane Marchesin ff9a019cf0 nouveau: add pure nv30 support. 2007-09-06 02:47:06 +02:00
Maarten Maathuis ef4944de85 Add context init voodoo and context switch code for NV41. 2007-09-04 18:51:57 +02:00
Ian Romanick fee49e2071 Merge branch 'master' of ssh+git://git.freedesktop.org/git/mesa/drm into xgi-0-0-2 2007-08-31 10:54:55 -07:00
Ian Romanick bb3da88601 Acutally emit the IRQ (duh) when setting the fence post. 2007-08-31 10:48:13 -07:00
Stephane Marchesin bac3f49daa nouveau: nv04 context switching support. Works for starting X up at least. 2007-08-31 01:40:00 +02:00
Stephane Marchesin 69b11f44f0 nouveau: give nv03 the last cut. 2007-08-31 01:40:00 +02:00
Ian Romanick 9c5b9d458b Use ati_pcigart for PCI-e GART table handling. 2007-08-29 14:41:49 -07:00
Ian Romanick c46ffd6b29 Fix late night dumb-dumb mistake. 2007-08-29 00:23:30 -07:00
Ian Romanick 2bcd5b5e33 Use DRM_SPINLOCK / DRM_UNSPINLOCK macros. 2007-08-29 00:04:18 -07:00
Keith Packard c78e610fa4 Add register defines for hw binning 2007-08-28 12:23:51 -07:00
Dave Airlie 589707b765 drm: remove XFREE86_VERSION macros 2007-08-28 15:17:36 +10:00
Matthieu Castet a331d2e352 nouveau : add NV04_PGRAPH_TRAPPED_ADDR definition
- fix offset for nv04
- use it in nv10 graph ctx switch for getting next channel
- dump NV10_PGRAPH_TRAPPED_DATA_HIGH on nv10+
2007-08-26 20:48:32 +02:00
Matthieu Castet 4182fce408 nouveau : nv1x graph reworks
- add forgotten init value
- use the same PGRAPH_DEBUG than the blob
- remove init of ddx reg : it should be done with object
- better handle of channel destruction

hope I didn't break anything ;)
2007-08-25 22:10:45 +02:00
Patrice Mandin 502bbdbe14 nouveau: nv10: output a warning if last channel invalid, and switch to next 2007-08-25 00:12:58 +02:00
Patrice Mandin 9875011196 nouveau: nv10: check some NULL pointers inside context switch 2007-08-23 10:20:44 +02:00
Matthieu Castet 8645dac895 nouveau : fix some potential crashes with objects causing hash collision 2007-08-22 23:20:14 +02:00
Ben Skeggs 11c46afe75 nouveau/nv40: Preserve other bits in 0x400304/0x400310 like NVIDIA do. 2007-08-22 13:23:49 +10:00
Ben Skeggs a654c0341a nouveau/nv40: Dump extra info on ucode state if ctx switch fails. 2007-08-22 13:19:21 +10:00
Ben Skeggs 81eaff44c4 nouveau: NV4c ctx ucode.
Seems we already have a nv4c_ctx_init() somehow, a quick check shows the
ucode matches it still.
2007-08-22 13:09:27 +10:00
Ben Skeggs ae883c97ad nouveau/nv50: Correct thinko for 8800 chips + cleanup a bit. 2007-08-22 12:54:26 +10:00
Stephane Marchesin c8ee6a6cab nouveau: redo nv30_graph.c. Should work better, but we still lack a couple of cards. 2007-08-22 04:20:50 +02:00
Stephane Marchesin 76337bdb19 nouveau: fix the comment and debug message for PCIGART size 2007-08-22 04:20:50 +02:00
Ben Skeggs 03c0490129 nouveau: Add NV44 ctx ucode. Patch from stillunknown.
Microcode is similar enough to the NV4A one that it should be able to use
the same initial PGRAPH context.  One day this mess will go away, honest..
2007-08-21 02:23:21 +10:00
Ben Skeggs 216f1b0573 nouveau: Poke 0x2230 on NV47 also.
Makes 0x2220 work the same way as on NV40.
2007-08-21 02:18:27 +10:00
Patrice Mandin c8760c7999 Check also for Linux, as it's not supported on different OS 2007-08-19 18:45:01 +02:00
Patrice Mandin a122e7dabf Function pci_get_bus_and_slot needs 2.6.19 or later 2007-08-19 18:41:18 +02:00
Ian Romanick 3383e8bd6b Remove unnecessary include. 2007-08-17 10:53:18 -07:00
Ian Romanick 0d3c741df1 Forgot to add this file on the last commit. 2007-08-16 13:43:04 -07:00
Eric Anholt 0055fd5c35 Merge branch 'master' into bo-set-pin 2007-08-16 09:23:09 -07:00
Ben Skeggs 8a4d7f34d9 nouveau: Detect memory on NFORCE/NFORCE2 correctly. 2007-08-17 01:12:46 +10:00
Ian Romanick d8a800b63d Implement fence support. 2007-08-15 21:05:26 -07:00
Eric Anholt b668d6d905 Fix dev->agp->base initialization on BSD, and fix addmap range check on Linux.
With the previous linux commit, an AGP aperture at the end of the address space
would have wrapped to 0 and the test would have failed.
2007-08-15 14:29:31 -07:00