ac076cb9af
nouveau: Fill in context_init for nv10-nv3x.
...
Fill in the context with the values from PFIFO_CACH1. This should work from nv10 through the nv30 series.
2007-01-09 23:12:37 -05:00
ec12209c76
nouveau: Don't use DRIVER_USE_MTRR, we already setup our own mtrr over vram.
2007-01-10 04:42:09 +01:00
f6ba3b2603
ttm: make ttm alloc/free into alloc_pages/free_pages
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Add a vmalloc flag to the page flags
2007-01-09 15:51:29 +11:00
a70aedd5fc
novueau: try resource 3 if resource 2 is 0 length
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This happens on my NV43 PPC
2007-01-09 13:48:38 +11:00
deba42ef32
nouveau: fix nv4a context size.
2007-01-08 20:55:57 +01:00
22821cf01d
add export symbol for memory manager
2007-01-08 22:27:27 +11:00
d0080d71b9
nouveau: nv4a context support.
2007-01-08 05:02:40 +01:00
6eaa1272b4
Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm
2007-01-08 03:50:34 +01:00
5bf60c9d6c
i830: complete fix for i830 maps
2007-01-08 13:09:51 +11:00
26bf6d9b5b
nouveau: oops
2007-01-08 12:50:44 +11:00
128d87a3dd
nouveau: nv43 context stuff
2007-01-08 12:47:51 +11:00
b147c39263
drm: remove drm_follow_page, and drm_ioremap and ioremapfree
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This comes from the Re: [patch] paravirt: isolate module ops on lkml
It needs some testing, please report any regressions caused.
Signed-off-by: Dave Airlie <airlied@linux.ie>
2007-01-08 11:47:15 +11:00
fe5770b89e
fixup i810/i830 to use drm_core_ioremap instead of drm_ioremap
2007-01-08 11:46:54 +11:00
1f0f7d7a18
nouveau: fix a stupid bug from me.
2007-01-08 00:11:39 +01:00
faa4612299
nouveau: avoid allocating vram that's used as instance memory.
2007-01-08 00:44:02 +11:00
cd3711455e
nouveau: map pci resource 2 on >=nv40
2007-01-08 00:44:02 +11:00
31daf66962
Revert i915 drm driver name to i915; miniglx doesn't work otherwise
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Yes, this driver supports the new memory manager, that is indicated by the
version number being >= 1.7.
2007-01-06 17:40:50 -08:00
2851c9f5c6
Bump i915 minor for ARB_OC ioctl
2007-01-06 16:26:54 -08:00
f7180349fd
i915: ARB_Occlusion_query(MMIO ioctl) support.
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This adds a new ioctl for passing counter information from the chip back to
applications, these counters include the data needed to perform OC.
2007-01-06 16:22:08 -08:00
1f1714cf3d
nouveau: get c51 doing glxgears without the binary driver's help.
2007-01-06 18:05:21 +11:00
dbb0d979cc
nouveau: Use PMC_BOOT_0 to determine which ctx_voodoo to load.
2007-01-06 17:50:00 +11:00
528ab8ce40
nouveau: oops, we don't need OS_HAS_MTRR actually.
2007-01-05 20:59:45 +01:00
d99c7c27e2
Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm
2007-01-05 20:50:46 +01:00
025f281bbf
nouveau: Add an mtrr over the whole FB
2007-01-05 20:49:34 +01:00
0f95ddc428
Merge branch 'master' of git+ssh://matc@git.freedesktop.org/git/mesa/drm/
2007-01-05 19:41:12 +01:00
9d167f1f4b
Add basic pgraph context for nv10.
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It only fake a context switch : pgraph state are not save/restored.
2007-01-05 19:40:11 +01:00
f80659bc29
Cleanup the nv04 fifo code a bit.
2007-01-05 19:37:06 +01:00
4fe2858f53
i915: Fix a DRM_ERROR that should be DRM_DEBUG.
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It would clutter up the kernel output in a situation which is legitimate before
X.org 7.2 and handled correctly by the 3D driver.
2007-01-02 10:05:48 +01:00
176b62991a
Make git ignore Emacs style backup files and cscope files.
2007-01-02 10:03:56 +01:00
972074b5d6
linux-core: Make git ignore generated module symbol version files.
2007-01-02 10:02:44 +01:00
91855bb254
nouveau: oops, forgot to free RAMIN..
2007-01-02 16:35:00 +11:00
861017e6d5
nouveau: Hookup nv40_graph_init.
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Now I can get 3D + working grctx switching on my NV40 without
the binary driver initialising the card first. However, this
change also breaks 3D on my C51 even *with* the binary driver's
help. So, it's likely that the weird voodoo is card-specific.
2007-01-02 15:56:10 +11:00
41da9fd2e5
nouveau: Hook up grctx code for NV4x.
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This is enough to get grctx switching going on my NV40 and C51 after
the binary driver has initialised the card first.
Bumping the drm patchlevel because the ddx needs some modifications to
have NV4x work at all with these changes.
2007-01-02 15:08:04 +11:00
0e0d954584
nouveau: Add nv40-specific PGRAPH code, not hooked up yet.
2007-01-02 14:52:43 +11:00
2c3bc69ba2
nouveau: Only clobber PFIFO if no channels are already alloc'd
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With this change the GPU is responsible for doing the channel switch
itself. This is needed for the upcoming NV4x PGRAPH context work as
we don't yet know enough to manually swap PGRAPH contexts.
2007-01-02 14:41:34 +11:00
2dcbf6a599
make build against 2.6.20 hopefully
2007-01-01 11:30:38 +11:00
87faf62fae
fixup permission along line of kernel
2007-01-01 11:22:35 +11:00
a16a8a47cd
Add some new via chipsets.
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Disable 3D functionality and AGP DMA for chipsets with the DX9 3D engine.
2006-12-28 22:17:08 +01:00
7859bd61d3
Leftover from previous commit.
2006-12-27 19:46:46 +01:00
2980ec22a1
Allow for non-power-of-two texture pitch alignment.
2006-12-27 19:38:33 +01:00
975136d6e5
Proper allocation of AGP pages for ttms.
2006-12-27 15:32:09 +01:00
c38ede0667
nouveau: return the *actual* type of memory alloc'd to userspace
2006-12-27 01:58:57 +11:00
9e019df757
nouveau: Alloc cmdbuf for each channel individually
2006-12-26 23:30:26 +11:00
72cb361c5c
Bug #9120 .
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Require at least agpgart version 0.102 for the AGP TTM backend.
This should hopefully avoid crashes when the wrong agpgart
driver is installed.
2006-12-21 12:05:49 +01:00
ae58225613
Improve memory manager accounting printout formatting.
2006-12-21 10:43:47 +01:00
a467d24829
Fix buggy aligned allocations.
2006-12-21 10:43:46 +01:00
b7586ab539
nouveau: save/restore endianness flag on FIFO switch
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This makes my G5 survive glxinfo and nouveau_demo - airlied
2006-12-21 17:47:10 +11:00
9acd4a13f2
Remove the stupid root_node field from the core memory manager.
2006-12-20 19:33:50 +01:00
672593f611
Replace vmalloc_32.
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The vmalloc_32 function together with the memset to clear
the new pages are replaced with a vmalloc_user.
A pre-2.6.18 compat vmalloc_user is added.
Please replace any breakage on machines with > 1GB of memory.
2006-12-20 14:40:36 +01:00
3b47b27558
Some via PCI posting flushes.
2006-12-20 13:04:21 +01:00
Jeremy Kolb jkolb@brandeis.edu
Stephane Marchesin
Dave Airlie
Ben Skeggs
Christoph Hellwig
Dave Airlie
Keith Packard
Wang Zhenyu
Zou Nan hai
Matthieu Castet
Michel Dänzer
Thomas Hellstrom
Ben Skeggs