Commit Graph

3208 Commits (4d83a751b421ec3f3e0c572070c3bc295b9adbcc)

Author SHA1 Message Date
Ian Romanick 4d83a751b4 drm-gem: Fix build
On some distros missing prototypes cause kernel builds to fail.  These
are hack to make the code build.
2008-07-18 12:42:43 -07:00
Eric Anholt f5c2f00e2f intel-gem: Leave 8xx tiling on until we find any issues. 2008-07-18 12:10:41 -07:00
Eric Anholt 78f1fc9cbc intel-gem: Disable tiling if we get junk from the MCHBAR read.
One of our systems has been returning 0xffffffff from all MCHBAR reads, which
means we'll need to figure out why, or add an alternate detection method.
2008-07-14 09:16:45 -07:00
Eric Anholt a0474be4e7 intel-gem: Add two new ioctls for managing tiling on objects.
Various chips have exciting interactions between the CPU and the GPU's
different ways of accessing interleaved memory, so we need some kernel
assistance in determining how it works.

Only fully tested on GM965 so far.
2008-07-11 18:58:02 -07:00
Eric Anholt 1f9a5307ac [intel-gem] typo fix in DRM_ERROR 2008-07-07 12:49:01 -07:00
Keith Packard d250a55fc6 [intel] Get vblank pipe from irq_mask_reg instead of hardware enable reg
With the interrupt enable/disable using only the mask register, it was wrong
to use the enable register to detect which pipes had vblank detection
turned on. Also, as we keep a local copy of the mask register around, and
MSI machines smack the hardware during the interrupt handler, it is more
efficient and more correct to use the local copy.
2008-06-24 13:39:25 -07:00
Keith Packard e36da6a133 [intel] Create functions to enable/disable interrupts
This shares common code sequences for managing the interrupt register bits
2008-06-24 13:08:04 -07:00
Keith Packard ce2effbe2d Merge branch 'drm-gem' into drm-gem-965 2008-06-24 10:03:05 -07:00
Keith Packard 2c6feb7a5a [intel-gem] Include drm_compat.h to get kmap_atomic_prot_pfn 2008-06-24 09:52:43 -07:00
Keith Packard c0043155ad drm_compat: it's CONFIG_HIGHMEM, not CONFIG_HIMEM
A mis-spelled config option (was it spelled that way in the past?)
eliminated kmap_atomic_prot_pfn from core DRM.
2008-06-24 09:52:33 -07:00
Keith Packard 5540457fa5 [intel-gem] Use I915_GEM_DOMAIN_GTT in dri_gem_bo_wait_rendering.
I915_GEM_DOMAIN_CPU is very expensive to wait for -- it generally requires
clflushing the frame buffer.
2008-06-24 09:52:27 -07:00
Keith Packard ed73651d47 [intel-gem] Recover resources from wedged hardware.
Clean up queues, free objects. On the next entervt, unmark the hardware to
let the user try again (presumably after resetting the chip). Someday we'll
automatically recover...
2008-06-24 09:52:14 -07:00
Keith Packard 71d975072c [intel-gem] pwrite through GTT
Pin/copy_from_user/unpin through the GTT to eliminate clflush costs.
Benchmarks say this helps quite a bit.
2008-06-24 09:52:05 -07:00
Keith Packard 01a33d742c Was using irq_enable_reg in the use_mask_reg path 2008-06-24 09:46:51 -07:00
Keith Packard 472981a4a9 [intel-gem] Include drm_compat.h to get kmap_atomic_prot_pfn 2008-06-23 22:03:33 -07:00
Keith Packard 020a59e46c drm_compat: it's CONFIG_HIGHMEM, not CONFIG_HIMEM
A mis-spelled config option (was it spelled that way in the past?)
eliminated kmap_atomic_prot_pfn from core DRM.
2008-06-23 22:03:06 -07:00
Keith Packard 52bf2e77b0 [intel-gem] Use I915_GEM_DOMAIN_GTT in dri_gem_bo_wait_rendering.
I915_GEM_DOMAIN_CPU is very expensive to wait for -- it generally requires
clflushing the frame buffer.
2008-06-23 11:21:30 -07:00
Keith Packard 27f61d0c93 [intel] leave interrupts disabled in ISR only on MSI again
While debugging the 915, I tried this trick there and accidentally left it
set.
2008-06-23 11:20:17 -07:00
Keith Packard 626e9ba494 [intel-gem] Recover resources from wedged hardware.
Clean up queues, free objects. On the next entervt, unmark the hardware to
let the user try again (presumably after resetting the chip). Someday we'll
automatically recover...
2008-06-23 10:16:35 -07:00
Keith Packard 1c2dd98267 [intel] Switch to using IMR instead of IER 2008-06-23 10:07:47 -07:00
Keith Packard 61caf797ae [intel-gem] pwrite through GTT
Pin/copy_from_user/unpin through the GTT to eliminate clflush costs.
Benchmarks say this helps quite a bit.
2008-06-23 00:53:53 -07:00
Keith Packard a0ebcbe9d4 [intel] allow the irq code to use either enable or mask registers
still not sure which works best on which hardware; this will make it easier
to experiment.
2008-06-23 00:53:04 -07:00
Keith Packard a369bf0e57 [intel] Use IMR instead of IER to pend interrupts during ISR
Noting that the interrupt mask register was more reliable than the interrupt
enable register for managing interrupts in user_irq_on/user_irq_off, this
patch replaces the remaining IER frobbing with IMR instead.

The test which exposes IER related failures is:

$ glxgears & glxgears & glxgears
(reposition the glxgears windows away from the upper left corner)
$ while :; do x11perf -rect100 -reps 800 -repeat 1; sleep 1; done &
$ while :; do runoa; runet; done &
2008-06-21 00:33:07 -07:00
Keith Packard 8be6ec491f [intel-gem] Add /proc/dri/*/i915_gem_interrupt
This tracks most of the interrupt-related status, including the
interrupt registers in the chip and the sequence number variables.
2008-06-21 00:13:18 -07:00
Keith Packard 33114e4a11 [intel] Count received interrupts
Another patch adds this to a /proc/dri file for debugging and monitoring.
2008-06-21 00:12:21 -07:00
Keith Packard f4bd566e0b [intel-gem] Remove unused variable. 2008-06-21 00:10:10 -07:00
Keith Packard 54817317e9 [intel-gem] Use polling in i915_gem_idle instead of interrupts.
While waiting for the hardware to idle on leavevt or lastclose, poll
for the sync sequence number instead of waiting for an interrupt. This
allows the code to bail if the hardware hangs for some reason. Also, this
avoids issues with signals as the exisiting wait function is interruptible.
2008-06-20 21:10:42 -07:00
Keith Packard 71b1623e22 [intel-gem] Add intel-specific /proc entries to help monitor gem operation
This adds gem_active, gem_flushing, gem_inactive, gem_request and gem_seqno
entries to monitor gem operation and help debug issues.
2008-06-20 21:07:46 -07:00
Keith Packard 2bd9799e4c Add device-specific proc_init and proc_cleanup hooks
This allows device drivers to add proc files
2008-06-20 16:40:14 -07:00
Keith Packard 918420deef [intel-gem] Use shmem_getpage instead of find_or_create_page
find_or_create_page doesn't quite set up pages correctly; any newly created
pages aren't hooked into the shmem object quite right; user space mmaps of
those pages end up mapping pages full of zeros which then get written to the
real pages inappropriately. This patch requires that the kernel export
shmem_getpage.
2008-06-20 00:21:57 -07:00
Keith Packard 52e5d24fae [intel-gem] Add DRM_IOCTL_I915_GEM_SW_FINISH to flag CPU writes
When a software fallback has completed, usermode must notify the kernel so
that any scanout buffers can be synchronized. This ioctl should be called
whenever a fallback completes to flush CPU and chipset caches.
2008-06-20 00:21:57 -07:00
Eric Anholt e7424e4580 [intel] Quirk away MSI support on 945G/GM.
The PCI caps register reports MSI support even though it isn't really there.
2008-06-16 15:15:02 -07:00
Eric Anholt c847271179 [linux] Use the device's irq for handler setup instead of stale dev->irq.
This fixes registration when MSI is set up after the stub function fills in
dev->irq.  Otherwise /proc/interrupts would report attachment to the fasteoi
interrupt.  dev->irq is still exposed (and updated at IRQ setup)
for the drivers that use it for whatever reason.
2008-06-16 15:09:11 -07:00
Keith Packard 3e48e14499 [intel-gem] Execute MI_FLUSH in leavevt_ioctl
In leavevt_ioctl, queue an MI_FLUSH and then block waiting for it to
complete. This will empty the active and flushing lists. That leaves only
the inactive list to evict.
2008-06-13 19:49:47 -07:00
Keith Packard 19c3418848 [intel-gem] inactive list may contain objects in CPU write domain
Pin/unpin need to know whether to remove/add objects from the inactive list,
inactive objects cannot be in any GPU write domain as those would be on the
flushing list instead. However, inactive objects may be in the CPU write
domain.
2008-06-13 19:47:23 -07:00
Keith Packard 93c2871ecc [intel-gem] BUG_ON active objects in gem_object_unbind
Now that gem_object_unbind waits for rendering to complete, objects should
not be active when they are being pulled from the GTT. BUG_ON if this is
broken.
2008-06-13 19:43:40 -07:00
Keith Packard 68856b619b [intel-gem] Debugging -- verify inactive list invariants
Inactive list elements may not be pinned, active or have non-CPU write
domains.
2008-06-13 19:40:16 -07:00
Keith Packard 732b196074 [intel-gem] whitespace fixes 2008-06-13 19:37:44 -07:00
Keith Packard a7139cb851 [intel-gem] show total GTT space in /proc/dri/*/gem_objects 2008-06-13 19:35:22 -07:00
Keith Packard 73bc18cad8 [intel-gem] Wait for rendering to complete before unbinding.
Moving to the CPU domain doesn't ensure that rendering is finished, the
buffer may still be in use as a texture or other data source.
2008-06-13 17:06:35 -07:00
Keith Packard 8b9ab108ec [libdrm] Restart all ioctls on signal receipt
Receiving a signal should be ignored by the library, so just restart any
ioctl which returns EINTR or EAGAIN.
2008-06-13 16:03:22 -07:00
Keith Packard 217beb9c8d [intel-gem] add gtt and pin counts to /proc/dri/*/gem_objects
Not quite portable, but these are useful for intel. Some more general
mechanism could be done...
2008-06-13 15:43:02 -07:00
Keith Packard 4086cdb655 [intel-gem] Left the last exec buffer pinned. oops.
Loop end variable 'pinned' was set one too low.
2008-06-13 15:38:13 -07:00
Keith Packard baf5213694 [intel-gem] Pin objects during execbuffer
Pinning the objects avoids accidentally evicting them while binding
other objects.
2008-06-13 14:29:46 -07:00
Keith Packard ced9ebf645 [intel-gem] throttle based on frames rather than time. Reduces jitter.
Record the last execbuffer sequence for each client.
Record that sequence in the throttle ioctl as the 'throttle sequence'.
Wait for the last throttle sequence in the throttle ioctl.
2008-06-13 14:29:46 -07:00
Keith Packard 6b2cba1ecc [intel-gem] evict_something was failing when wait_request freed objects
When i915_wait_request clears object from the active list, it may end up
freeing them and not moving them to the inactive list. This ends up
unbinding objects from the GTT without there ever being new objects visible
to i915_gem_evict_something on the inactive list. As the only success
condition required the presence of objects on the inactive list, this would
falsely assume that no GTT space had been made available, and end up
returning -ENOMEM to the application.
2008-06-13 14:29:46 -07:00
Keith Packard 3762c9ea67 [intel] Enable MSI for i915 IRQ 2008-06-13 14:29:46 -07:00
Keith Packard 5957470ca3 [intel] Restructure irq to pend all work until after iir write.
The interrupt identity register must be writen before any work occurs lest
we drop an interrupt on the floor. This patch just shuffles code around to
make sure that IIR is written as early as possible.
2008-06-13 14:29:46 -07:00
Keith Packard 462af73149 [intel-gem] Use a delayed_work instead of a timer + work_struct
We want request retirement to occur about once a second when the request
queue is non-empty. This was done with a timer that queued a work_struct,
using a delayed_work instead makes a lot more sense.
2008-06-13 14:29:46 -07:00
Keith Packard e5364914ac [intel-gem] Reorder i915_add_request to schedule work last
i915_add_request was calling schedule_delayed_work before adding the request
to the list; it makes more sense to do that last.
2008-06-13 14:29:45 -07:00