Commit Graph

1631 Commits (5052e966ec7fe5146c2d73b90482003619add5da)

Author SHA1 Message Date
Kristian Høgsberg 5052e966ec Merge commit 'origin/master' into modesetting-gem
Conflicts:
	linux-core/Makefile.kernel
	linux-core/ati_pcigart.c
	linux-core/drm_compat.h
	linux-core/drm_irq.c
	linux-core/drm_lock.c
	linux-core/i915_drv.c
	shared-core/i915_dma.c
	shared-core/i915_drv.h
	shared-core/i915_irq.c
	shared-core/nouveau_mem.c
	shared-core/radeon_cp.c
	shared-core/radeon_drv.h
2008-07-31 15:18:32 -04:00
Dave Airlie 95c02743c9 i915: more version checks 2008-07-30 16:52:13 +10:00
Dave Airlie 02b09d271c i915: add version checks for opregion on old kernels 2008-07-30 16:26:59 +10:00
Nicolai Haehnle 90b90c65dc r300: Fix cliprect emit
This makes our handling of cliprects sane. drm_clip_rect always has exclusive
bottom-right corners, but the hardware expects inclusive bottom-right corners,
so we adjust this here.

This complements Michel Daenzer's commit 57aea290e1e0a26d1e74df6cff777eb9f038f1f8
to Mesa. See also http://bugs.freedesktop.org/show_bug.cgi?id=16123 .
2008-07-29 19:59:08 +02:00
Stuart Bennett 6b903f5edf nouveau: fix nv04 fifo context save to save reg contents, not reg offset
clearly the function had never been used :)
2008-07-29 02:32:13 +01:00
Stuart Bennett 591f6bcba3 nouveau: fix bad rename from 5a072f32c8 2008-07-29 02:26:34 +01:00
Nicolai Haehnle c3d463840c r300_cmdbuf: Always emit INDX_BUFFER immediately after DRAW_INDEX
DRAW_INDEX writes a vertex count to VAP_VF_CNTL. Docs say that behaviour
is undefined (i.e. lockups happen) when this write is not followed by the
right number of vertex indices.

Thus we used to do the wrong thing when drawing across many cliprects was
necessary, because we emitted a sequence
 DRAW_INDEX, DRAW_INDEX, INDX_BUFFER, INDX_BUFFER
instead of
 DRAW_INDEX, INDX_BUFFER, DRAW_INDEX, INDX_BUFFER
The latter is what we're doing now and which ought to be correct.
2008-07-26 16:40:51 +02:00
Dave Airlie df9871064e radeon: add initial atombios modesetting and GEM -> TTM translation layer.
This is an initial import of the atom bios parser with modesetting support
for r500 hw using atombios. It also includes a simple memory manager
layer that translates a radeon GEM style interface onto TTM internally.

So far this memory manager has only been used for pinned object allocation
for the DDX to test modesetting.
2008-07-26 08:56:23 +10:00
Dave Airlie fb05c4d621 Merge remote branch 'origin/modesetting-101' into modesetting-gem 2008-07-26 08:38:59 +10:00
Robert Noland 965a72202b i915: Move all of the irq install/uninstall to load time.
This resolves a panic on FreeBSD which was caused by trying
to re-initialize the swap lock.  It's just much easier to
initialize all of the locks at load time.  It should also
ensure that the vblank structures are available earlier.
2008-07-23 19:55:06 -04:00
Dave Airlie 589f968173 radeon: fix typo with a better typo 2008-07-22 18:47:27 +10:00
Dave Airlie c669489813 radeon: fix type DST vs Z cache flush 2008-07-22 18:10:03 +10:00
Michel Dänzer b5cddbcc15 Remove accidental leftover tests.
Thanks to Nicolai Haehnle for pointing this out on IRC.
2008-07-21 13:43:12 +02:00
Michel Dänzer e4feaf506d radeon: Post-vblank-rework-rework cleanups.
Thanks to the reworked vblank-rework, we can just use the hardware frame
counter directly, and make the RADEON_PARAM_VBLANK_CRTC getparam just return
what was set by the corresponding setparam.
2008-07-21 08:16:59 +02:00
Maarten Maathuis 65803e53a6 modesetting-101: implement optional scaling and dithering properties 2008-07-20 13:49:18 +02:00
Jesse Barnes 04893aa99a i915: convert to using drm_vblank_get/put around vblank counter usage
All interrupt off vblank count updates are done in drm_vblank_get/put
now, so convert users of the vblank counter over to that interface.
2008-07-19 13:21:38 -04:00
Ben Skeggs 0ef097b598 nv50: use same dma object for fb/tt access
We depend on the VM fully now for memory protection, separate DMA objects
for VRAM and GART are unneccesary.  However, until the next interface break
(soon) a client can't depend on the objects being the same and must still
call NV_OBJ_SET_DMA_* methods appropriately.
2008-07-18 18:25:33 +02:00
Ben Skeggs 4872ac9c62 nouveau: interface changes for nv5x 3d 2008-07-18 17:44:51 +02:00
Dave Airlie 7cfdba2b30 radeon: remove microcode version 2008-07-18 14:36:47 +10:00
Dave Airlie ed7e170915 drm/radeon: fixup 0 vs NULL 2008-07-18 14:32:46 +10:00
Jesse Barnes a9427cf318 i915: remove old broken vblank code
Remove the unused (and broken) "in vblank" code now that the core has
been fixed to use a counter while interrupts are enabled.  Also make the
vblank pipe get/set ioctls into dumb stub functions, since with the new
code we can no longer let userspace control whether vblank interrupts
are enabled, or the core code will misbehave.
2008-07-17 13:55:24 -04:00
Hong Liu dfd441cf96 This is a modified version of Hong's patch from last month, with a few
modifications to make it work correctly on my test hardware (altered the
backlight write function, made it enable the legacy backlight controller
interrupts on mobile hardware, sorted the interrupt function so we don't
get an excessive number of vblank interrupts). This lets the backlight
keys on my T61 work properly, though there's a 750msec or so delay
between the request and the brightness actually changing - this sounds
awfully like the hardware spinning waiting for a status flag to become
ready, but as far as I can tell they're all set correctly. If anyone can
figure out what's wrong here, it'd be nice to know.

Some of the functions are still stubs and just tell the hardware that
the request was successful. These can be filled in as kernel modesetting
gets integrated. I think it's worth getting this in anyway, since it's
required for backlight control to work properly on some new platforms.

Signed-off-by: Matthew Garrett <mjg@redhat.com>
2008-07-15 10:14:17 -07:00
Dave Airlie abdd523c75 drm: add fix for PAT on radeon with 2.6.26 2008-07-15 16:18:22 +10:00
Dave Airlie 2556341f8b Merge remote branch 'origin/modesetting-101' into modesetting-gem 2008-07-09 14:53:47 +10:00
Ben Skeggs c7ed2c6791 nouveau: interface changes for nv5x 3d 2008-07-08 12:35:50 +10:00
Kristian Høgsberg 38a5f6686c Add back flink, open and close ioctls.
They fell through the cracks in 86accbcb.
2008-07-07 18:00:23 -04:00
Kristian Høgsberg 3e02f7fd31 Merge commit 'origin/drm-gem' into ms-gem
Conflicts:

	linux-core/drmP.h
	linux-core/drm_drv.c
	linux-core/drm_stub.c
	linux-core/i915_drv.c
	linux-core/i915_gem.c
	shared-core/i915_drv.h
	shared-core/i915_irq.c
2008-07-07 15:43:43 -04:00
Maarten Maathuis 6738e7b00b modesetting-101: Rename DPMS modes to avoid compatibility issues with xorg definitions. 2008-07-06 11:08:49 +02:00
Maarten Maathuis e810cb9243 modesetting-101: rename modeflags, as to avoid conflicts with the xorg definitions 2008-07-06 10:52:25 +02:00
Maarten Maathuis 7cbc5f6145 modesetting-101: Make the interface variable names a little more consistent + modeprint changes.
- All things are now called _id when they are id's.
- modeprint now accepts driver name as first argument.
2008-07-05 12:04:07 +02:00
Maarten Maathuis c9915d695d modesetting-101: Move some defines used for enumeration into the public header.
- Otherwise userspace has no idea of the meaning.
2008-07-04 17:28:04 +02:00
Dave Airlie 142a309604 modesetting: rip out all of the generation code.
not needed, hotplug will work just as well hopefully.
2008-07-04 09:34:24 +10:00
Maarten Maathuis 062d850620 nv50: s/FALSE/false && s/TRUE/true 2008-07-03 09:08:01 +02:00
Zhenyu Wang 401f77a2ef i915: official name for GM45 chipset
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
2008-07-03 00:49:51 +08:00
Maarten Maathuis f1fe9178f1 NV50: basic fbcon + misc fixes
- There is one fb, used for as many outputs as possible.
- Eventually smaller screens will be scaled to see the full console, but for the moment this'll do.
2008-07-02 16:14:48 +02:00
Jesse Barnes 301d984ea8 i915: only use tiled blits on 965+
When scheduled swaps occur, we need to blit between front & back buffers.  I
the buffers are tiled, we need to set the appropriate XY_SRC_COPY tile bit,
only on 965 chips, since it will cause corruption on pre-965 (e.g. 945).

Bug reported by and fix tested by Tomas Janousek <tomi@nomi.cz>.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-07-01 16:10:01 -07:00
Maarten Maathuis bc32d1798a NV50: some i2c cleanup 2008-07-01 15:14:30 +02:00
Maarten Maathuis 91c742663a NV50: use list_head item instead of list_head head to avoid confusion 2008-06-27 18:58:13 +02:00
Maarten Maathuis 4d85d5d251 NV50: i misunderstood NOUVEAU_MEM_INTERNAL, so remove it 2008-06-25 15:27:07 +02:00
Maarten Maathuis 09b67dda0b NV50: Some cleanup and fixes. 2008-06-25 15:16:38 +02:00
Ben Skeggs be72762816 nv50: when destroying a channel make sure it's not still current on PFIFO
We won't get a PFIFO context switch when the same channel ID is recreated if
the hw still thinks the channel is already active, which causes fun issues.

Should allow X to be stopped and started without tearing down the entire
card state in lastclose().
2008-06-25 09:55:19 +02:00
Ben Skeggs 5a0164d1e1 nouveau: allocate drm-use vram buffers from end of vram.
This avoids seeing garbage from engine setup etc before X gets around
to pointing the CRTCs at a new scanout buffer.  Not actually a noticable
problem before G80 as PRAMIN is forced to the end of VRAM by the hardware
already.
2008-06-25 09:55:14 +02:00
Ben Skeggs 5d27fd94af nv50: when destroying a channel make sure it's not still current on PFIFO
We won't get a PFIFO context switch when the same channel ID is recreated if
the hw still thinks the channel is already active, which causes fun issues.

Should allow X to be stopped and started without tearing down the entire
card state in lastclose().
2008-06-25 16:49:48 +10:00
Keith Packard d250a55fc6 [intel] Get vblank pipe from irq_mask_reg instead of hardware enable reg
With the interrupt enable/disable using only the mask register, it was wrong
to use the enable register to detect which pipes had vblank detection
turned on. Also, as we keep a local copy of the mask register around, and
MSI machines smack the hardware during the interrupt handler, it is more
efficient and more correct to use the local copy.
2008-06-24 13:39:25 -07:00
Keith Packard e36da6a133 [intel] Create functions to enable/disable interrupts
This shares common code sequences for managing the interrupt register bits
2008-06-24 13:08:04 -07:00
Jesse Barnes 893cd01a1d i915: register definition & header file cleanup
It would be nice if one day the DRM driver was the canonical source for
register definitions and core macros.  To that end, this patch cleans things up
quite a bit, removing redundant definitions (some with different names
referring to the same register) and generally tidying up the header file.
2008-06-24 12:51:29 -07:00
Keith Packard ed73651d47 [intel-gem] Recover resources from wedged hardware.
Clean up queues, free objects. On the next entervt, unmark the hardware to
let the user try again (presumably after resetting the chip). Someday we'll
automatically recover...
2008-06-24 09:52:14 -07:00
Maarten Maathuis 30f153a7c2 nouveau: disable KMS for pre-NV50 even when specifically enabled 2008-06-22 19:31:55 +02:00
Ben Skeggs 01e8f0ea42 nv50: oops, keep VRAM allocations aligned at 64KiB - that's our page size.. 2008-06-23 02:42:15 +10:00
Ben Skeggs 89cf2ee2e5 nv50: use same dma object for fb/tt access
We depend on the VM fully now for memory protection, separate DMA objects
for VRAM and GART are unneccesary.  However, until the next interface break
(soon) a client can't depend on the objects being the same and must still
call NV_OBJ_SET_DMA_* methods appropriately.
2008-06-23 01:24:11 +10:00