Commit Graph

3076 Commits (50bce2bc625deb439dd61f504496dddd0cd4f572)

Author SHA1 Message Date
Eric Anholt 50bce2bc62 [intel-gem] Only update obj->write_domain if we're actually changing it.
The problem was revealed where on 965, the display list vertex buffer would see:

create		      -> (CPU, CPU)
set_domain (CPU, CPU) -> (CPU, CPU)
set_comain (CPU, 0)   -> (CPU, 0) (no clflush occurred)
execbuf	   (GPU, 0)   -> (CPU+GPU, 0) (still no clflush)

instead of:

create		      -> (CPU, CPU)
set_domain (CPU, CPU) -> (CPU, CPU)
set_comain (CPU, 0)   -> (CPU, CPU)
execbuf	   (GPU, 0)   -> (CPU+GPU, 0) (clflushed)
2008-05-30 13:47:34 -07:00
Eric Anholt 4f92ed3427 [intel-gem] Add an option to check GTT versus CPU coherency at execbuf time. 2008-05-30 12:42:48 -07:00
Eric Anholt 3b1e4e6dc3 [intel-gem] Write the presumed_offset back out after updating it.
Otherwise, 965 constant state buffers get re-relocated every exec.  Ouch.
2008-05-29 12:53:21 -07:00
Keith Packard 19ff3366e4 [intel-gem] Clean up active/inactive/flushing list debugging. 2008-05-28 23:56:31 -07:00
Eric Anholt e10502002f [intel-gem] Replace idlelock usage with real lock acquisition. 2008-05-27 18:03:18 -07:00
Keith Packard 1f4e36081b [intel-gem] Must hold DRM lock while setting object domain
Object domain transfer can involve adding flush ops to the request queue,
and so the DRM lock must be held to avoid having the X server smash pointers
badly.
2008-05-26 17:41:46 -07:00
Keith Packard d434b64f6a [i915] leave interrupts masked off when not in use.
The interrupt enable register cannot be used to temporarily disable
interrupts, instead use the interrupt mask register.

Note that this change means that a pile of buffers will be left stuck on the
chip as the final interrupts will not be recognized to come and drain things.
2008-05-26 03:25:16 -07:00
Keith Packard 7cf3fd29fe [intel-gem] Add DRM_I915_GEM_BUSY ioctl to check for idle buffers.
This new ioctl returns whether re-using the buffer would force a wait.
2008-05-25 20:45:20 -07:00
Keith Packard 6d1d11704a [intel-gem] Compute npages instead of nbytes in flush_pwrite
i915_gem_flush_pwrite optimizes short writes to the buffer by clflushing
only the modified pages, but it was miscomputing the number of pages.
2008-05-25 20:44:19 -07:00
Keith Packard c69b81df62 [intel-gem] replace call to jiffies_to-msec with simple inline 2008-05-25 20:41:42 -07:00
Keith Packard 8c2b207f9b [intel-gem] Encourage multiple caches to hold read data
When reading from multiple domains, allow each cache to continue
to hold data until writes occur somewhere. This is done by
first leaving the read_domains alone at bind time (presumably the CPU read
cache contains valid data still) and then in set_domain, if no write_domain
is specified, the new read domains are simply merged into the existing read
domains.

A huge comment was added above set_domain to explain how things are
expected to work.
2008-05-22 23:08:38 -07:00
Keith Packard 44ed693ca6 [gem] Use CPU domain for new or pageable objects
Newly allocated objects need to be in the CPU domain as they've just been
cleared by the CPU. Also, unmapping objects from the GTT needs to put them
into the CPU domain, both to flush rendering as well as to ensure that any
paging action gets flushed before we remap to the GTT.
2008-05-22 22:00:21 -07:00
Keith Packard 71b09a5f75 [intel-gem] Force ring retire by emiting flush before user-interrupt.
Commands in the ring are parsed and started when the head pointer passes by
them, but they are not necessarily finished until a MI_FLUSH happens. This
patch inserts a flush after the execbuffer (the only place a flush wasn't
already happening).
2008-05-22 22:00:21 -07:00
Keith Packard a51c3a76ff [intel] Add debug code to verify the cached ring tail pointer.
Recording the tail pointer in a local variable improves performance, but if
someone messes up and fails to reload at the right time, the driver will
write commands to the wrong part of the ring and scramble execution badly.

This change (available by setting I915_RING_VALIDATE to 1) checks to make
sure the cached tail pointer matches the hardware tail pointer at each ring
buffer addition, calling BUG_ON when that's not true.
2008-05-22 22:00:21 -07:00
Keith Packard da3f099a7c [intel-gem] invalidate ring locals for pin/unpin/set_domain/free functions
Ring locals must be reloaded from hardware in case the X server ran.
2008-05-22 22:00:21 -07:00
Eric Anholt 5e662f90d1 [gem] Release GEM buffers from work task scheduled from IRQ.
There are now 3 lists.  Active is buffers currently in the ringbuffer.
Flushing is not in the ringbuffer, but needs a flush before unbinding.
Inactive is as before.  This prevents object_free → unbind →
wait_rendering → object_reference and a kernel oops about weird refcounting.

This also avoids an synchronous extra flush and wait when freeing a buffer
which had a write_domain set (such as a temporary rendered to and then from
using the 2d engine).  It will sit around on the flushing list until the
appropriate flush gets emitted, or we need the GTT space for another
operation.
2008-05-22 22:00:21 -07:00
Eric Anholt d6f7968577 [gem] Replace ring throttling hack with actual time measurement. 2008-05-21 16:40:14 -07:00
Eric Anholt 54fa32cdfe [gem] Fix bad test for list_for_each completion.
Since it's a circular list, the entry won't be NULL at termination.
2008-05-21 15:15:58 -07:00
Eric Anholt 7078978db0 [gem] Hold a reference on the object in i915_gem_wait_space.
Otherwise, in the middle of the function called using it the last ref
might disappear.
2008-05-21 15:04:07 -07:00
Keith Packard f8e38e49dd [intel-gem] invalidate ring locals for pin/unpin/set_domain/free functions
Ring locals must be reloaded from hardware in case the X server ran.
2008-05-21 15:00:16 -07:00
Eric Anholt af8e087157 [gem] Use a separate sequence number field from classic/ttm
This lets us get some qualities we desire, such as using the full 32-bit
range (except zero), avoiding DRM_WAIT_ON, and a 1:1 mapping of active
sequence numbers to request structs, which will be used soon for throttling
and interrupt-driven list cleanup.
2008-05-20 14:16:26 -07:00
Eric Anholt ab36a6f983 [gem] Rename sequence numbers from "cookie" to "seqno" 2008-05-20 10:53:10 -07:00
Eric Anholt 6c3ac484b0 [gem] Clean up active/inactive list handling using helper functions.
Additionally, a boolean active field is added to indicate which list an
object is on, rather than smashing last_rendering_cookie to 0 to show
inactive.  This will help with flush-reduction later on, and makes the code
clearer.
2008-05-20 10:52:39 -07:00
Eric Anholt 7dced2f33a [gem] Hold dev->struct_mutex to protect structure data. 2008-05-15 18:45:23 -07:00
Eric Anholt 3ab152da66 [gem] Rename the GTT LRU lists to active (executing) and inactive (idle). 2008-05-15 11:59:58 -07:00
Eric Anholt aafafe507b [gem] typo fix in comment. 2008-05-15 11:59:57 -07:00
Eric Anholt 6e46a3c762 [GEM] Update testcases for new API. 2008-05-12 15:42:20 -07:00
Eric Anholt f650d7240a [GEM] Typo (and thinking) fixes in drm-gem.txt and doxygen. 2008-05-12 13:17:01 -07:00
Keith Packard 17e8000ac0 [intel] Minor kludge -- wait for the ring to be nearly empty before queuing
No need to fill the ring that much; wait for it to become nearly empty
before adding the execbuffer request. A better fix will involve scheduling
ring insertion in the irq handler.
2008-05-12 13:04:18 -07:00
Keith Packard 7e7ea313c4 [intel] When polling for ring space, sleep for a lot longer (10ms)
If the ring is full, the engine will surely be running for more than 10ms.
2008-05-12 13:03:16 -07:00
Keith Packard 6aeff6b9e3 [gem] Set write domain to CPU when doing pwrite.
Leave the flush call in place, which can fix domains up if necessary.
2008-05-12 13:01:57 -07:00
Keith Packard 6950b7da71 [gem] Clarify use of explicit domain control. Remove Gen3 from I-cache usage. 2008-05-12 13:00:55 -07:00
Keith Packard ff39db099b [GEM] Make pread/pwrite manage memory domains. No luck with movnti though.
pread and pwrite must update the memory domains to ensure consistency with
the GPU. At some point, it should be possible to avoid clflush through this
path, but that isn't working for me.
2008-05-11 00:10:16 -07:00
Keith Packard 1b0bf30143 [intel-GEM] exec list can contain pinned, lru cannot.
The exec list contains all objects, in order of use. The lru list contains
only unpinned objects ready to be evicted. This required two changes -- the
first was to not migrate pinned objects from exec to lru, the second was to
search for the first unpinned object in the exec list when doing eviction.
2008-05-10 22:04:39 -07:00
Keith Packard 1f9eaceb71 Merge commit 'anholt/drm-gem' into drm-gem 2008-05-10 21:05:25 -07:00
Keith Packard 177b8b0703 [GEM] Add drm-gem.txt
Add some API and implementation documentation for GEM.
2008-05-10 21:04:42 -07:00
Keith Packard a37ac493da [intel-GEM] Clean up GEM ioctl naming.
Rename 'validate_entry' to 'exec_object', then clean up some field names in
structures (renaming buffer_offset to just offset, for example).
2008-05-10 21:04:18 -07:00
Eric Anholt 48a8531aa4 GEM: Fix arguments to drm_memrange_init so we don't exceed our allocation.
It takes (offset, size), not (offset, end).
2008-05-09 18:23:51 -07:00
Eric Anholt c5c59eab80 GEM: Separate the LRU into execution list and LRU list.
Now, the LRU list has objects that are completely done rendering and ready
to kick out, while the execution list has things with active rendering,
which have associated cookies and reference counts on them.
2008-05-09 17:38:32 -07:00
Eric Anholt f56f2acb5a GEM: Clear obj_priv->agp_mem when we free it.
Still managing to get something wrong with this, oopsing down in agp.
2008-05-09 15:07:49 -07:00
Eric Anholt f0ae335cd7 GEM: Avoid leaking refs on target objects on presumed offset success. 2008-05-09 15:02:50 -07:00
Keith Packard 1e26ca44c9 [gem] API cleanup. allocate->create unreference->close name->flink
Make the API names a bit more consistent.
2008-05-09 12:18:09 -07:00
Keith Packard ec75369b40 [i915] clean up whinging from checkpatch.pl 2008-05-08 13:09:17 -07:00
Keith Packard 07ad5ce1e1 Clean up whinging from checkpatch.pl in drm_gem.c
Whitespace changes, a few too-long-lines and some extra braces.
2008-05-08 13:08:22 -07:00
Eric Anholt 2f573e6df4 GEM: Fix oops on NULL dereference when we try clflushing when we don't need to. 2008-05-08 12:46:02 -07:00
Keith Packard 9af4c49743 [intel-gem] Move domains to relocation records. add set_domain ioctl.
Domain information is about buffer relationships, not buffer contents. That
means a relocation contains the domain information as it knows how the
source buffer references the target buffer.

This also adds the set_domain ioctl so that user space can move buffers to
the cpu domain.
2008-05-08 10:44:02 -07:00
Eric Anholt effc6d998f GEM: fix testcases for new ioctl args. 2008-05-07 16:00:58 -07:00
Arjan van de Ven aa0621a19f Apply a few stylistic cleanups to match kernel code. 2008-05-07 15:54:53 -07:00
Eric Anholt 06e9761f94 GEM: Wait for existing rendering to complete before writing relocation data.
This should already have been generally safe since we don't change contents
and put in new relocations between execbufs, so if we were writing in a new
relocation then we'd already waited rendering to complete when we moved
the target of the relocation.  However, doing the right thing will be required
if we do buffer reuse.
2008-05-07 14:10:04 -07:00
Eric Anholt 5f5f01ed91 GEM: Extend cache domain stuff for 965.
One of our MI_FLUSH bits is reserved on 965, being always implied, and there's
a vertex cache that was forgotten.
2008-05-07 12:46:06 -07:00