Patch allows the backlight to be manipulated under gnome on apple powerpc
based NV30 machines. It works fine on my powerbook, and should also work
for older NV17/NV18 machines.
Note that older powerpc specific tools (pbbuttonsd) have some problems with
this implementation (because the device is not yet there at the start time
of the daemon, and the code makes incorrect assumptions about the max
brightness values). However, IMHO these things can and should be addressed
in the daemon.
Some style/warning fixes applied by Stuart Bennett <stuart@freedesktop.org>
This wraps the new DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID ioctl,
allowing applications to discover the pipe number corresponding
to a given CRTC ID. This is necessary for doing pipe-specific
operations such as waiting for vblank on a given CRTC.
NV04 was completely busted. Push buffers were getting allocated at the
end of VRAM, overwriting PRAMIN. So, it turns out PRAMIN is in VRAM on
all chips. Question answered!
Several nvidia-based systems don't support backlight control via the
standard ACPI control mechanisms. Instead, it's necessary for the driver
to modify the backlight control registers directly. This patch adds
support for determining whether the registers appear to be in use, and
if so registers a kernel backlight device to control them. The backlight
can then be controlled via existing userspace tools.
Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
NVIDIA do this fun little sequence after updating the PRAMIN page tables.
On 9xxx chips, none of the PRAMIN BAR bindings (except the initial one)
worked, hence the majority of the setup needed to create a channel
ended up in the wrong place, causing all sorts of fun.
This is done by NVIDIA on nv8x chips also, so we'll do it for them too,
even though they appear to work without it.
I'm not 100% sure that the nv94 one we were using won't work. The context
layouts are identical (well.. same ctxprog, so of course!), only a couple
of registers differ. But, be safe until we actually get some 9xxx chips
working.
Our PFIFO/PGRAPH context save/load functions don't really work well
(at all?) on nv5x yet. Depending on what random state the card is
in before the drm loads, fbcon probably won't work correctly.
Luckily we've setup the GPU in such a way that it'll actually do a
hw context switch for the first context. Not sure of how successful
this'd be currently on the older chips (actually, pretty sure it won't
work), so NV50 only for now.
This patch tries to use the available fence count to figure out whether a
given batch can succeed or not (just like the aperture check).
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
The values are really going to continue meaning pipe, not plane, and that's
what they're called in the kernel copy of the header. Userland hasn't ever
made the switch to pipe!=plane, since userland checks are based on DRM
version, which is still stuck at 1.6. However, Mesa did start using
plane[AB] names, so provide a compat define.
Add mode setting files to libdrm, including xf86drmMode.* and the new
drm_mode.h header. Also add a couple of tests to sanity check the
kernel interfaces and update code to support them.
I either messed up when I pulled these from a mmio-trace last time, or
the previous values didn't work on my card. Hopefully it's the former!
In any case, at least one of the original NV50 chipsets work now.
A small subset of CS need to be atomic (relocation+IB commit to
ring) right now, because of the way relocation are handled, we
need to protect the whole ioctl.
Ben Skeggs
Danny Tholen
Carl Worth
Alan Coopersmith
Stuart Bennett
Robert Noland
Pekka Paalanen
Matthew Garrett
Ben Skeggs
Stephane Marchesin
Stuart Bennett
Jesse Barnes
Dave Airlie
Eric Anholt
Jerome Glisse