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9 Commits (74001c34e5ad768feec8b2fbe9a617bc598a0a4b)

Author SHA1 Message Date
Ben Skeggs a46104674f nouveau/nv50: demagic instmem setup. 2007-08-10 14:22:50 +10:00
Ben Skeggs beaa0c9a28 nouveau: Pass channel struct around instead of channel id. 2007-08-06 03:40:43 +10:00
Ben Skeggs 0029713451 nouveau: nuke internal typedefs, and drm_device_t use. 2007-07-13 15:09:31 +10:00
Ben Skeggs c806bba466 nouveau/nv50: Initial channel/object support 
Should be OK on G84 for a single channel, multiple channels *almost* work.

Untested on G80.
 2007-07-09 16:16:44 +10:00
Ben Skeggs 163f852612 nouveau: rewrite gpu object code 
Allows multiple references to a single object, needed to support PCI(E)GART
scatter-gather DMA objects which would quickly fill PRAMIN if each channel
had its own.

Handle per-channel private instmem areas.  This is needed to support NV50,
but might be something we want to do on earlier chipsets at some point?

Everything that touches PRAMIN is a GPU object.
 2007-07-09 16:16:44 +10:00
Ben Skeggs e26ec51146 nouveau: small RAMFC cleanups 2007-06-29 14:20:50 +10:00
Ben Skeggs 68ecf61647 nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bit 2007-06-28 03:26:44 +10:00
Ben Skeggs 4f2dd78ff3 nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaks 2007-06-28 03:04:48 +10:00
Ben Skeggs 05d86d950a nouveau: NV04 PFIFO engtab functions 2007-06-24 18:57:09 +10:00