Commit Graph

6864 Commits (7b67fec649b07cd5ded66814ba799b09b4d407c8)

Author SHA1 Message Date
Keith Packard d434b64f6a [i915] leave interrupts masked off when not in use.
The interrupt enable register cannot be used to temporarily disable
interrupts, instead use the interrupt mask register.

Note that this change means that a pile of buffers will be left stuck on the
chip as the final interrupts will not be recognized to come and drain things.
2008-05-26 03:25:16 -07:00
Keith Packard 7cf3fd29fe [intel-gem] Add DRM_I915_GEM_BUSY ioctl to check for idle buffers.
This new ioctl returns whether re-using the buffer would force a wait.
2008-05-25 20:45:20 -07:00
Keith Packard 6d1d11704a [intel-gem] Compute npages instead of nbytes in flush_pwrite
i915_gem_flush_pwrite optimizes short writes to the buffer by clflushing
only the modified pages, but it was miscomputing the number of pages.
2008-05-25 20:44:19 -07:00
Keith Packard c69b81df62 [intel-gem] replace call to jiffies_to-msec with simple inline 2008-05-25 20:41:42 -07:00
Jesse Barnes 9fc4ea5c00 i915: do a better job of parsing VBIOS data
Add code to get panel modes from the VBIOS if present and check whether certain
outputs exist.  Should make our display detection code a little more robust.
2008-05-23 18:42:47 -07:00
Jesse Barnes b4d8cda8e6 drm_mode_debug_printmodeline doesn't need struct drm_device *
Makes printing modelines from some routines easier.
2008-05-23 18:41:58 -07:00
Keith Packard 8c2b207f9b [intel-gem] Encourage multiple caches to hold read data
When reading from multiple domains, allow each cache to continue
to hold data until writes occur somewhere. This is done by
first leaving the read_domains alone at bind time (presumably the CPU read
cache contains valid data still) and then in set_domain, if no write_domain
is specified, the new read domains are simply merged into the existing read
domains.

A huge comment was added above set_domain to explain how things are
expected to work.
2008-05-22 23:08:38 -07:00
Keith Packard 44ed693ca6 [gem] Use CPU domain for new or pageable objects
Newly allocated objects need to be in the CPU domain as they've just been
cleared by the CPU. Also, unmapping objects from the GTT needs to put them
into the CPU domain, both to flush rendering as well as to ensure that any
paging action gets flushed before we remap to the GTT.
2008-05-22 22:00:21 -07:00
Keith Packard 71b09a5f75 [intel-gem] Force ring retire by emiting flush before user-interrupt.
Commands in the ring are parsed and started when the head pointer passes by
them, but they are not necessarily finished until a MI_FLUSH happens. This
patch inserts a flush after the execbuffer (the only place a flush wasn't
already happening).
2008-05-22 22:00:21 -07:00
Keith Packard a51c3a76ff [intel] Add debug code to verify the cached ring tail pointer.
Recording the tail pointer in a local variable improves performance, but if
someone messes up and fails to reload at the right time, the driver will
write commands to the wrong part of the ring and scramble execution badly.

This change (available by setting I915_RING_VALIDATE to 1) checks to make
sure the cached tail pointer matches the hardware tail pointer at each ring
buffer addition, calling BUG_ON when that's not true.
2008-05-22 22:00:21 -07:00
Keith Packard da3f099a7c [intel-gem] invalidate ring locals for pin/unpin/set_domain/free functions
Ring locals must be reloaded from hardware in case the X server ran.
2008-05-22 22:00:21 -07:00
Eric Anholt 5e662f90d1 [gem] Release GEM buffers from work task scheduled from IRQ.
There are now 3 lists.  Active is buffers currently in the ringbuffer.
Flushing is not in the ringbuffer, but needs a flush before unbinding.
Inactive is as before.  This prevents object_free → unbind →
wait_rendering → object_reference and a kernel oops about weird refcounting.

This also avoids an synchronous extra flush and wait when freeing a buffer
which had a write_domain set (such as a temporary rendered to and then from
using the 2d engine).  It will sit around on the flushing list until the
appropriate flush gets emitted, or we need the GTT space for another
operation.
2008-05-22 22:00:21 -07:00
Dave Airlie 49075b678f r500: add two more register ranges for mesa driver to setup 2008-05-23 09:40:26 +10:00
Dave Airlie 74a9ea896e drm: fix nouveau warning 2008-05-23 09:40:26 +10:00
Hong Liu 1cde3cc1ac i915: check dummy page before freeing
The dummy read page will point to NULL if drm_bo_driver_init failed at
firstopen (modeset is not enabled), and will cause kernel oops at
subsequent drm_lastclose call, so be sure to check it.
2008-05-22 10:35:55 -07:00
Hong Liu e8320a716d i915: init bo mm at driver init only when modeset=1
To avoid bo memory manager being inited twice, it will be called
at firstopen when modeset is not enabled.
2008-05-22 10:34:08 -07:00
Eric Anholt d6f7968577 [gem] Replace ring throttling hack with actual time measurement. 2008-05-21 16:40:14 -07:00
Eric Anholt 54fa32cdfe [gem] Fix bad test for list_for_each completion.
Since it's a circular list, the entry won't be NULL at termination.
2008-05-21 15:15:58 -07:00
Eric Anholt 7078978db0 [gem] Hold a reference on the object in i915_gem_wait_space.
Otherwise, in the middle of the function called using it the last ref
might disappear.
2008-05-21 15:04:07 -07:00
Keith Packard f8e38e49dd [intel-gem] invalidate ring locals for pin/unpin/set_domain/free functions
Ring locals must be reloaded from hardware in case the X server ran.
2008-05-21 15:00:16 -07:00
Dave Airlie 91c6c4b240 rs690/r500: vblank support.
The new display controller has the vblank interrupts in a different place.

Add support for vbl interrupts for these chips
2008-05-21 21:27:33 +10:00
Eric Anholt af8e087157 [gem] Use a separate sequence number field from classic/ttm
This lets us get some qualities we desire, such as using the full 32-bit
range (except zero), avoiding DRM_WAIT_ON, and a 1:1 mapping of active
sequence numbers to request structs, which will be used soon for throttling
and interrupt-driven list cleanup.
2008-05-20 14:16:26 -07:00
Eric Anholt ab36a6f983 [gem] Rename sequence numbers from "cookie" to "seqno" 2008-05-20 10:53:10 -07:00
Eric Anholt 6c3ac484b0 [gem] Clean up active/inactive list handling using helper functions.
Additionally, a boolean active field is added to indicate which list an
object is on, rather than smashing last_rendering_cookie to 0 to show
inactive.  This will help with flush-reduction later on, and makes the code
clearer.
2008-05-20 10:52:39 -07:00
Dave Airlie 8399656106 r500: add more register ranges for Mesa driver 2008-05-17 10:22:12 +10:00
Eric Anholt 7dced2f33a [gem] Hold dev->struct_mutex to protect structure data. 2008-05-15 18:45:23 -07:00
Eric Anholt 3ab152da66 [gem] Rename the GTT LRU lists to active (executing) and inactive (idle). 2008-05-15 11:59:58 -07:00
Eric Anholt aafafe507b [gem] typo fix in comment. 2008-05-15 11:59:57 -07:00
Dave Airlie a09c0bbe11 ati_pcigart: oops wrong way around not that it actually mattered 2008-05-14 22:48:12 +10:00
Dave Airlie 4c6ec02eb8 ati_pcigart: stop working in the evenings you mess up too often 2008-05-14 22:44:22 +10:00
Dave Airlie 2712cdeec3 Revert "ati_pcigart: fixup properly this version might even work"
This reverts commit bc0836e12a.

tree has some kref hacks in it - oops
2008-05-14 22:43:28 +10:00
Dave Airlie bc0836e12a ati_pcigart: fixup properly this version might even work 2008-05-14 22:42:21 +10:00
Dave Airlie dd1f33f83c ati_pcigart: fill out 40-bit gart table support properly
Thanks to Alex for supplying this info.
2008-05-14 22:35:32 +10:00
Alex Deucher caace3692f RS4xx: separate out RS400 and RS480 IGP chips
RS400 (intel based IGP) and RS480 (AMD based IGP) have
different MC and GART setups.  Currently we only support
RS480.
2008-05-13 21:02:17 -04:00
Jesse Barnes e4f29968f4 Merge branch 'modesetting-101' of ssh://git.freedesktop.org/git/mesa/drm into modesetting-101 2008-05-13 14:47:17 -07:00
Jesse Barnes ee631e1b86 i915: register definition & header file cleanup
It would be nice if one day the DRM driver was the canonical source for
register definitions and core macros.  To that end, this patch cleans
things up quite a bit, removing redundant definitions (some with
different names referring to the same register) and generally tidying up
the header file.
2008-05-13 14:44:17 -07:00
Jakob Bornecrantz 5be53a0881 i915: execbuf now works without i915_dma_init being called 2008-05-13 09:26:26 +02:00
Jesse Barnes d32ce7f621 i915: TV hotplug fixes
In order to avoid recursive ->detect->interrupt->detect->interrupt->...
we need to disable TV hotplug interrupts in
intel_tv.c:intel_tv_detect_type.  We also need to enable the TV interrupt
detection and hotplug sequence properly in i915_irq.c.
2008-05-12 15:47:19 -07:00
Eric Anholt 6e46a3c762 [GEM] Update testcases for new API. 2008-05-12 15:42:20 -07:00
Eric Anholt f650d7240a [GEM] Typo (and thinking) fixes in drm-gem.txt and doxygen. 2008-05-12 13:17:01 -07:00
Keith Packard 17e8000ac0 [intel] Minor kludge -- wait for the ring to be nearly empty before queuing
No need to fill the ring that much; wait for it to become nearly empty
before adding the execbuffer request. A better fix will involve scheduling
ring insertion in the irq handler.
2008-05-12 13:04:18 -07:00
Keith Packard 7e7ea313c4 [intel] When polling for ring space, sleep for a lot longer (10ms)
If the ring is full, the engine will surely be running for more than 10ms.
2008-05-12 13:03:16 -07:00
Keith Packard 6aeff6b9e3 [gem] Set write domain to CPU when doing pwrite.
Leave the flush call in place, which can fix domains up if necessary.
2008-05-12 13:01:57 -07:00
Keith Packard 6950b7da71 [gem] Clarify use of explicit domain control. Remove Gen3 from I-cache usage. 2008-05-12 13:00:55 -07:00
Hong Liu a51e38548c fix kernel oops when removing fb
drm_crtc->fb may point to NULL, f.e X server will allocate a new fb
and assign it to the CRTC at startup, when X server exits, it will destroy
the allocated fb, making drm_crtc->fb points to NULL.
2008-05-12 12:31:56 -07:00
Hong Liu b2dee13f5d free dummy read page if fail to init mm
Since drm_bo_driver_init will be called in driver_load, we need to free
what it alloced when error to avoid memory leak.
2008-05-12 12:07:27 -07:00
Hong Liu f1b9bbe2b8 modeset init code cleanup
moving modeset init code into one function and correct error
handling druing i915 init
2008-05-12 12:07:04 -07:00
Hong Liu af60d87869 fix G33 hardware status page in modeset
We need to alloc a hw status page bo for G33 if modeset is enabled since the 2D
driver can't alloc gfx memory when working in drm modeset.
2008-05-12 12:04:02 -07:00
Alex Deucher 10d754f0a2 RADEON: fix copy/pasto in last commit 2008-05-12 14:49:43 -04:00
Alex Deucher 75bc739bee R3/4/5: init pipe setup in drm
Similar (broken) code in mesa needs to be removed
2008-05-12 09:44:20 -04:00