Commit Graph

4014 Commits (9dff806802bad79242c58cc5dca3fd108099982b)

Author SHA1 Message Date
Jie Luo e935925cd7 i915: enable bus mastering on i915 at resume time
On 9xx chips, bus mastering needs to be enabled at resume time for much of the
chip to function.  With this patch, vblank interrupts will work as expected
on resume, along with other chip functions.   Fixes kernel bugzilla #10844.

Signed-off-by: Jie Luo <clotho67@gmail.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2008-07-01 12:22:54 -07:00
Maarten Maathuis 2b9c5719c0 NV50: switch to fixed point scale factor calculations 2008-07-01 16:00:09 +02:00
Maarten Maathuis bc32d1798a NV50: some i2c cleanup 2008-07-01 15:14:30 +02:00
Maarten Maathuis 91c742663a NV50: use list_head item instead of list_head head to avoid confusion 2008-06-27 18:58:13 +02:00
Maarten Maathuis 9f28da80f6 Change some obviously wrong things about property blobs, still broken though.
- I do not fully understand these blobs, so i'm leaving it at this for the moment.
2008-06-27 18:45:08 +02:00
Maarten Maathuis 71906e86e8 [modesetting-101] Actually store properties when being changed. 2008-06-27 16:30:25 +02:00
Maarten Maathuis 01ee5eda9a NV50: A minor change. 2008-06-27 01:29:30 +02:00
Maarten Maathuis 701011224c NV50: Implement DPMS. 2008-06-27 01:16:36 +02:00
Maarten Maathuis d88616555d [modesetting-101] tab-cleanup 2008-06-26 23:21:01 +02:00
Maarten Maathuis 087e3f577d Revert "modesetting-101: Make dpms property optional + misc cleanup."
This reverts commit 13943fe582.
2008-06-26 23:12:04 +02:00
Maarten Maathuis 13943fe582 modesetting-101: Make dpms property optional + misc cleanup.
- intel_crt seems the only one to provide it, so init it there.
2008-06-26 21:28:29 +02:00
Maarten Maathuis 4d85d5d251 NV50: i misunderstood NOUVEAU_MEM_INTERNAL, so remove it 2008-06-25 15:27:07 +02:00
Maarten Maathuis 09b67dda0b NV50: Some cleanup and fixes. 2008-06-25 15:16:38 +02:00
Ben Skeggs be72762816 nv50: when destroying a channel make sure it's not still current on PFIFO
We won't get a PFIFO context switch when the same channel ID is recreated if
the hw still thinks the channel is already active, which causes fun issues.

Should allow X to be stopped and started without tearing down the entire
card state in lastclose().
2008-06-25 09:55:19 +02:00
Ben Skeggs 5a0164d1e1 nouveau: allocate drm-use vram buffers from end of vram.
This avoids seeing garbage from engine setup etc before X gets around
to pointing the CRTCs at a new scanout buffer.  Not actually a noticable
problem before G80 as PRAMIN is forced to the end of VRAM by the hardware
already.
2008-06-25 09:55:14 +02:00
Ben Skeggs 5d27fd94af nv50: when destroying a channel make sure it's not still current on PFIFO
We won't get a PFIFO context switch when the same channel ID is recreated if
the hw still thinks the channel is already active, which causes fun issues.

Should allow X to be stopped and started without tearing down the entire
card state in lastclose().
2008-06-25 16:49:48 +10:00
root d55629a13d silence warning 2008-06-24 23:18:29 +01:00
Keith Packard d250a55fc6 [intel] Get vblank pipe from irq_mask_reg instead of hardware enable reg
With the interrupt enable/disable using only the mask register, it was wrong
to use the enable register to detect which pipes had vblank detection
turned on. Also, as we keep a local copy of the mask register around, and
MSI machines smack the hardware during the interrupt handler, it is more
efficient and more correct to use the local copy.
2008-06-24 13:39:25 -07:00
Keith Packard e36da6a133 [intel] Create functions to enable/disable interrupts
This shares common code sequences for managing the interrupt register bits
2008-06-24 13:08:04 -07:00
Jesse Barnes d726eb2e5e i915: remove unused variable
Leftover dev_priv from the move of the suspend/resume code into shared-core.
2008-06-24 12:57:21 -07:00
Jesse Barnes 893cd01a1d i915: register definition & header file cleanup
It would be nice if one day the DRM driver was the canonical source for
register definitions and core macros.  To that end, this patch cleans things up
quite a bit, removing redundant definitions (some with different names
referring to the same register) and generally tidying up the header file.
2008-06-24 12:51:29 -07:00
Maarten Maathuis 5dbcb7551f NV50: minor change 2008-06-24 20:29:08 +02:00
Keith Packard ce2effbe2d Merge branch 'drm-gem' into drm-gem-965 2008-06-24 10:03:05 -07:00
Keith Packard 2c6feb7a5a [intel-gem] Include drm_compat.h to get kmap_atomic_prot_pfn 2008-06-24 09:52:43 -07:00
Keith Packard c0043155ad drm_compat: it's CONFIG_HIGHMEM, not CONFIG_HIMEM
A mis-spelled config option (was it spelled that way in the past?)
eliminated kmap_atomic_prot_pfn from core DRM.
2008-06-24 09:52:33 -07:00
Keith Packard 5540457fa5 [intel-gem] Use I915_GEM_DOMAIN_GTT in dri_gem_bo_wait_rendering.
I915_GEM_DOMAIN_CPU is very expensive to wait for -- it generally requires
clflushing the frame buffer.
2008-06-24 09:52:27 -07:00
Keith Packard ed73651d47 [intel-gem] Recover resources from wedged hardware.
Clean up queues, free objects. On the next entervt, unmark the hardware to
let the user try again (presumably after resetting the chip). Someday we'll
automatically recover...
2008-06-24 09:52:14 -07:00
Keith Packard 71d975072c [intel-gem] pwrite through GTT
Pin/copy_from_user/unpin through the GTT to eliminate clflush costs.
Benchmarks say this helps quite a bit.
2008-06-24 09:52:05 -07:00
Keith Packard 01a33d742c Was using irq_enable_reg in the use_mask_reg path 2008-06-24 09:46:51 -07:00
Maarten Maathuis 14522b3e1b NV50: fix a few misc things 2008-06-24 12:38:57 +02:00
Maarten Maathuis 315fef7ee4 NV50: fix cursor hide/show 2008-06-24 10:16:52 +02:00
Maarten Maathuis e7582cfff6 NV50: These are actually errors. 2008-06-24 09:41:13 +02:00
Keith Packard 472981a4a9 [intel-gem] Include drm_compat.h to get kmap_atomic_prot_pfn 2008-06-23 22:03:33 -07:00
Keith Packard 020a59e46c drm_compat: it's CONFIG_HIGHMEM, not CONFIG_HIMEM
A mis-spelled config option (was it spelled that way in the past?)
eliminated kmap_atomic_prot_pfn from core DRM.
2008-06-23 22:03:06 -07:00
Maarten Maathuis 5072a2911e NV50: fix some misc bugs 2008-06-24 00:00:02 +02:00
Maarten Maathuis 246b41fea4 [modesetting-101] update mode count after fill_modes.
- This avoids returning with a mode count of 0, thus not allocating space for the 2nd ioctl.
2008-06-23 22:59:17 +02:00
Maarten Maathuis f9dad8cc22 libdrm: check for allocation failure 2008-06-23 21:15:54 +02:00
Maarten Maathuis 0a45f15066 NV50: Improve set_config and fix some minor bugs. 2008-06-23 20:33:32 +02:00
Keith Packard 52bf2e77b0 [intel-gem] Use I915_GEM_DOMAIN_GTT in dri_gem_bo_wait_rendering.
I915_GEM_DOMAIN_CPU is very expensive to wait for -- it generally requires
clflushing the frame buffer.
2008-06-23 11:21:30 -07:00
Keith Packard 27f61d0c93 [intel] leave interrupts disabled in ISR only on MSI again
While debugging the 915, I tried this trick there and accidentally left it
set.
2008-06-23 11:20:17 -07:00
Keith Packard 626e9ba494 [intel-gem] Recover resources from wedged hardware.
Clean up queues, free objects. On the next entervt, unmark the hardware to
let the user try again (presumably after resetting the chip). Someday we'll
automatically recover...
2008-06-23 10:16:35 -07:00
Keith Packard 1c2dd98267 [intel] Switch to using IMR instead of IER 2008-06-23 10:07:47 -07:00
Keith Packard 61caf797ae [intel-gem] pwrite through GTT
Pin/copy_from_user/unpin through the GTT to eliminate clflush costs.
Benchmarks say this helps quite a bit.
2008-06-23 00:53:53 -07:00
Keith Packard a0ebcbe9d4 [intel] allow the irq code to use either enable or mask registers
still not sure which works best on which hardware; this will make it easier
to experiment.
2008-06-23 00:53:04 -07:00
Maarten Maathuis 30f153a7c2 nouveau: disable KMS for pre-NV50 even when specifically enabled 2008-06-22 19:31:55 +02:00
Maarten Maathuis b0b0f37443 NV50: Fix a few more possible leaks. 2008-06-22 19:04:22 +02:00
Maarten Maathuis 7c9551a464 fix typo 2008-06-22 18:58:04 +02:00
Maarten Maathuis e67cd7dda9 NV50: A few minor added safeties + cleanup. 2008-06-22 18:47:51 +02:00
Ben Skeggs 01e8f0ea42 nv50: oops, keep VRAM allocations aligned at 64KiB - that's our page size.. 2008-06-23 02:42:15 +10:00
Ben Skeggs 89cf2ee2e5 nv50: use same dma object for fb/tt access
We depend on the VM fully now for memory protection, separate DMA objects
for VRAM and GART are unneccesary.  However, until the next interface break
(soon) a client can't depend on the objects being the same and must still
call NV_OBJ_SET_DMA_* methods appropriately.
2008-06-23 01:24:11 +10:00