83199c257e
Fix missing \n on some DRM_ERROR in i915_dma.c
2007-10-24 16:27:51 -07:00
fd7c24753c
i915: use a drm memory barrier define
2007-10-24 11:13:15 +11:00
a294aa724a
i915: require mfence before submitting batchbuffer
2007-10-23 17:54:07 +10:00
9a115080e8
nouveau: fix IGP
2007-10-23 02:19:17 +02:00
919c886b2b
A cmdbuf mutex to implement validate-submit-fence atomicity in the absence
...
of a hardware lock.
2007-10-22 18:59:37 +02:00
22883ff26b
i915: split reloc execution into separate function
2007-10-22 11:54:41 +11:00
9ddff6d15f
Adapt i915 super-ioctl for lock-free operation.
2007-10-21 12:26:26 +02:00
3b19b50cb5
Remove the need for the hardware lock in the buffer manager.
...
Add interface entry cleaning a memory type without touching NO_EVICT buffers.
2007-10-21 12:20:56 +02:00
48b5eaf303
Simple replacement for hardware lock in some cases.
...
Fix i915 since last commit.
2007-10-20 16:49:43 +02:00
086c058a41
Remove the op ioctl, and replace it with a setuser ioctl.
...
Remove need for lock for now.
May create races when we clean memory areas or on takedown.
Needs to be fixed.
Really do a validate on buffer creation in order to avoid problems with
fixed memory buffers.
2007-10-17 10:59:48 +02:00
0d1926d36e
Revert "Replace NO_MOVE/NO_EVICT flags to buffer objects with an ioctl to set pinning."
...
This reverts cf2d569dac
2007-10-17 10:59:48 +02:00
646560d1d1
Revert "Add some more verbosity to drm_bo_set_pin_req comments."
...
This reverts e7bfeb3031
2007-10-17 10:59:48 +02:00
ec1162b212
i915: lock struct mutex about buffer object lookups
2007-10-17 15:36:14 +10:00
a69c85fec8
Drop destroy ioctls for fences and buffer objects.
...
We now always create a drm_ref_object for user objects and this is then the only
things that holds a reference to the user object. This way unreference on will
destroy the user object when the last drm_ref_object goes way.
2007-10-16 22:03:05 +11:00
dccefba71a
Take bo type argument out of the ioctl interface.
...
The buffer object type is still tracked internally, but it is no longer
part of the user space visible ioctl interface. If the bo create ioctl
specifies a non-NULL buffer address we assume drm_bo_type_user,
otherwise drm_bo_type_dc. Kernel side allocations call
drm_buffer_object_create() directly and can still specify drm_bo_type_kernel.
Not 100% this makes sense either, but with this patch, the buffer type
is no longer exported and we can clean up the internals later on.
2007-10-16 22:03:05 +11:00
440fc5113e
Eliminate support for fake buffers.
2007-10-16 21:59:38 +11:00
9fdab5b5c5
nouveau: revert unintended change.
2007-10-16 14:43:57 +11:00
677753047f
nouveau: Cleanup PGRAPH handler, attempt to survive PGRAPH exceptions.
2007-10-16 14:42:26 +11:00
3af053779c
nouveau: Survive PFIFO_CACHE_ERROR.
2007-10-16 13:32:03 +11:00
6398325ba1
nouveau: Handle multiple PFIFO exceptions per irq, cleanup output.
2007-10-16 13:27:27 +11:00
30353c8efc
nouveau: PPC fixes. These regs are very touchy.
2007-10-14 23:08:36 +02:00
837e364353
nouveau: fix warning.
2007-10-14 10:56:31 -04:00
811e43f9e2
nouveau: fix warning.
2007-10-14 10:56:17 -04:00
8d3cb7e472
i915: fix vbl_swap allocation
2007-10-14 21:19:13 +10:00
3ab7627651
nouveau: Fix a typo in nv25_graph_context_init
2007-10-12 23:55:59 +03:00
50deb31e9f
nouveau: Fix typos in nv20_graph_context_init
2007-10-12 23:49:51 +03:00
0d2554f83e
nouveau: Make notifiers go into PCI memory
...
On some hardware notifers in AGP memory just don't work.
2007-10-12 23:47:14 +03:00
9d779e2c88
nouveau: mandatory "oops I forgot half of the files" commit
2007-10-12 22:40:08 +02:00
74ea019863
nouveau: added support for software methods, and implemented those necessary for NV04 (TNT1) to start X
2007-10-12 22:36:55 +02:00
74001c34e5
i915: add superioctl support to i915
...
This adds the initial i915 superioctl interface. The interface should be
sufficent even if the implementation may needs fixes/optimisations internally
in the drm wrt caching etc.
2007-10-12 10:54:38 +10:00
bf126f4925
nouveau : nv10 and nv04 PGRAPH_NSTATUS are different
2007-10-10 21:11:43 +02:00
d912709a63
nouveau: PMC_BOOT_1 was not mapped.
2007-10-10 16:41:21 +02:00
9b294bbe0e
nouveau: try to fix big endian.
2007-10-10 01:12:20 +02:00
20928a2f2b
nouveau: A char is signed, so it may overflow for >NV50.
2007-10-07 19:01:58 +02:00
18952a1670
nouveau : print correct value in nouveau_graph_dump_trap_info for nv04
2007-10-06 12:01:02 +02:00
19b7cc3444
Merge branch 'pre-superioctl-branch'
2007-10-05 12:11:43 +10:00
d351601899
nouveau: Remove excess device classes.
2007-10-04 09:46:16 +02:00
319436c5cc
nouveau: NV47 context switching voodoo + warning
2007-10-04 09:39:31 +02:00
b510517d59
nouveau: Switch over to using PMC_BOOT_0 for card detection.
2007-10-04 09:31:46 +02:00
7fbd10d933
nouveau: nv2a drm context switch support.
2007-10-04 03:44:23 +02:00
a72eb27fbc
nouveau: nv20 graph_create_context difference
...
nv20 writes the chan->id to a different place than nv28.
This still does not make nv20 run nv10_demo.
2007-10-02 22:18:47 +03:00
afc57ef1df
nouveau: fix nv25_graph_context_init
...
It was writing 4x the data in a loop.
2007-10-02 22:18:47 +03:00
ffa3173ec4
nouveau: nv20 graph context init
2007-10-02 22:18:46 +03:00
69fcfb413e
nouveau: Fix dereferencing a NULL pointer when erroring out during initialization.
2007-10-01 22:21:23 +02:00
e1600646a9
nouveau: flip the ctx switch bit on. it seems to be ignored on nv34 but causes nv30 issues.
2007-10-01 03:28:10 +02:00
75e8f4b5cf
nouveau : nv30 remove harcoded NV20_PGRAPH_CHANNEL_CTX_TABLE
2007-09-30 23:19:39 +02:00
9cd6ece307
nouveau : nv20_graph replace nouveau_graph_wait_idle by nouveau_wait_for_idle
...
Also clean PGRAPH_CHANNEL macros
2007-09-30 23:09:30 +02:00
aa135ba8e8
nouveau: rename nv30_graph.c to nv20_graph.c
2007-09-30 22:16:01 +03:00
205403aea8
nouveau: nv30 graph function renames, removed nv20_graph.c
...
All nv30 functions in nv30_graph.c that can be used on nv20 are renamed
as accordingly. nv20 specific parts from nv20_graph.c are moved into
nv30_graph.c.
2007-09-30 22:16:01 +03:00
a67060c810
nouveau: graph ctx init nv25
...
According to mmio_trace_900XGL.tar.bz2 by Evan Fraser the nv25 init is
exactly the same as nv28 init.
2007-09-30 22:16:01 +03:00
aa2c337991
nouveau: nv28 graph context init
2007-09-30 22:16:01 +03:00
8ad605a264
nouveau: let nv20 hardware do ctx switching automatically.
2007-09-30 22:16:01 +03:00
dc592c8b7b
nouveau: Make nv20 use the nv30 PGRAPH ctx functions.
2007-09-30 22:16:01 +03:00
88bdb38cea
nouveau: Change couple constants to symbols.
2007-09-30 22:16:01 +03:00
a45fce7712
nouveau: NV30 should never call nouveau_nv20_context_switch().
2007-09-30 22:16:01 +03:00
fb3ed99fb1
nouveau : pgraph_ctx dynamic alloc for nv04, nv10
2007-09-30 14:50:22 +02:00
c76e04828b
nouveau : nv04 don't use chan->pgraph_ctx array
...
This commit is a first step to dynamic alloc pgraph context on nv04, nv10.
2007-09-30 14:21:47 +02:00
f8f31f0457
nouveau : stop the fifo of the channel we are deleting
2007-09-29 23:07:29 +02:00
097db7a9b0
nouveau : nv1x fix strange corruption
...
that appears when running glxgears and nouveau demo
2007-09-29 23:07:29 +02:00
f863d23e01
radeon: Commit the ring after each partial texture upload blit.
...
This makes sure each blit starts as early as possible, which may improve
texture upload performance in some cases.
2007-09-29 18:08:04 +02:00
72134e939e
nouveau : clean chan->pgraph_ctx stuff. We now do a static init of the array.
...
This avoid hardcoding pgraph_ctx size and potential buffer overflow.
2007-09-28 21:29:58 +02:00
0bb2395a8b
Revert drm_i915_flip_t braindamage
...
I should not have renamed this field.
I should not have renamed this field.
I should not have renamed this field.
On the plus side, it was at least binary compatible.
2007-09-28 10:10:08 -07:00
c4b3a0f602
Merge branch 'master' into pre-superioctl-branch
...
Conflicts:
linux-core/drm_bo.c
linux-core/drm_fence.c
linux-core/drm_objects.h
shared-core/drm.h
2007-09-25 18:03:31 +02:00
03c47f1420
drm: use fence_class as name instead of class
2007-09-25 16:17:17 +10:00
da63f4ba0f
Add fence error member.
...
Modify the TTM backend bind arguments.
Export a number of functions needed for driver-specific super-ioctls.
Add a function to map buffer objects from the kernel, regardless of where they're
currently placed.
A number of error fixes.
2007-09-22 13:57:13 +02:00
24e33627c5
Merge branch 'bo-set-pin'
...
This branch replaces the NO_MOVE/NO_EVICT flags to buffer validation with a
separate privileged ioctl to pin buffers like NO_EVICT meant before. The
functionality that was supposed to be covered by NO_MOVE may be reintroduced
later, possibly in a different way, after the superioctl branch is merged.
2007-09-21 17:12:19 -07:00
e7bfeb3031
Add some more verbosity to drm_bo_set_pin_req comments.
2007-09-21 16:14:22 -07:00
7587e9682c
nouveau: fix ppc and get it right this time.
2007-09-21 22:42:39 +02:00
dc60c452e6
nouveau: fix notifiers on PPC.
2007-09-21 22:27:53 +02:00
74c6f2f47a
nouveau: add some checks to the nv04 graph switching code.
2007-09-21 22:04:50 +02:00
3d3a96ad4e
Merge branch 'origin' into bo-set-pin
2007-09-19 15:55:58 -07:00
e349b58b4a
i915: Reinstate check that drawable has valid information in i915_vblank_swap.
2007-09-18 21:06:55 +01:00
78d111fa96
i915: Fix scheduled buffer swaps.
...
One instance of unlocking a spinlock was converted incorrectly when this code
was fixed to build on BSD.
2007-09-18 21:06:55 +01:00
a3881ad2fe
Add ioc32 compat layer for XGI DRM.
2007-09-18 11:03:49 -07:00
852232fb80
Remove plane->pipe mapping from SAREA private after all
...
We can figure out which pipe a given plane is mapped to by looking at the
display control registers instead of tracking it in a new SAREA private field.
If this becomes a performance problem, we could move to an ioctl based solution
by adding a new parameter for the DDX to set (defaulting to the old behavior if
the param was never set of course).
2007-09-12 08:55:33 -07:00
7fdf98051a
Merge branch 'master' of ssh://git.freedesktop.org/git/mesa/drm
2007-09-11 03:50:17 -07:00
3cb8acd5ab
Disambiguate planes & pipes for swap operations
...
This mod makes the SAREA track plane to pipe mappings and corrects the name of
the plane info variables (they were mislabeled as pipe info since until now all
code assumed a direct mapping between planes and pipes).
It also updates the flip ioctl argument to take a set of planes rather than
pipes, since planes are flipped while pipes generate vblank events.
2007-09-11 03:48:46 -07:00
0bd8752a0c
nouveau: nv10: add combiner registers
2007-09-10 18:53:48 +02:00
00bb534a54
nouveau : nv10 fix NV10_PGRAPH_CTX_USER save/load
2007-09-09 15:49:33 +02:00
b2ee72f440
nouveau : nv10 pipe ctx switch load/save.
...
This fix some issues with more than one 3D fifo, but there still some "corruption" sometimes
2007-09-09 12:13:00 +02:00
f19d80b046
nouveau: Add Quadro NVS 140 pciid
2007-09-08 22:19:00 +02:00
06bb072595
nouveau: Use nv41 ctxprog/vals on nv42.
2007-09-07 20:07:13 +10:00
54c96cbc46
Merge branch 'xgi-0-0-2'
2007-09-06 15:37:52 -07:00
edf5a86a26
nouveau: fix some nv04 graph switching.
2007-09-06 02:47:06 +02:00
ff9a019cf0
nouveau: add pure nv30 support.
2007-09-06 02:47:06 +02:00
ef4944de85
Add context init voodoo and context switch code for NV41.
2007-09-04 18:51:57 +02:00
fee49e2071
Merge branch 'master' of ssh+git://git.freedesktop.org/git/mesa/drm into xgi-0-0-2
2007-08-31 10:54:55 -07:00
bac3f49daa
nouveau: nv04 context switching support. Works for starting X up at least.
2007-08-31 01:40:00 +02:00
69b11f44f0
nouveau: give nv03 the last cut.
2007-08-31 01:40:00 +02:00
c78e610fa4
Add register defines for hw binning
2007-08-28 12:23:51 -07:00
589707b765
drm: remove XFREE86_VERSION macros
2007-08-28 15:17:36 +10:00
a331d2e352
nouveau : add NV04_PGRAPH_TRAPPED_ADDR definition
...
- fix offset for nv04
- use it in nv10 graph ctx switch for getting next channel
- dump NV10_PGRAPH_TRAPPED_DATA_HIGH on nv10+
2007-08-26 20:48:32 +02:00
4182fce408
nouveau : nv1x graph reworks
...
- add forgotten init value
- use the same PGRAPH_DEBUG than the blob
- remove init of ddx reg : it should be done with object
- better handle of channel destruction
hope I didn't break anything ;)
2007-08-25 22:10:45 +02:00
502bbdbe14
nouveau: nv10: output a warning if last channel invalid, and switch to next
2007-08-25 00:12:58 +02:00
9875011196
nouveau: nv10: check some NULL pointers inside context switch
2007-08-23 10:20:44 +02:00
8645dac895
nouveau : fix some potential crashes with objects causing hash collision
2007-08-22 23:20:14 +02:00
11c46afe75
nouveau/nv40: Preserve other bits in 0x400304/0x400310 like NVIDIA do.
2007-08-22 13:23:49 +10:00
a654c0341a
nouveau/nv40: Dump extra info on ucode state if ctx switch fails.
2007-08-22 13:19:21 +10:00
81eaff44c4
nouveau: NV4c ctx ucode.
...
Seems we already have a nv4c_ctx_init() somehow, a quick check shows the
ucode matches it still.
2007-08-22 13:09:27 +10:00
ae883c97ad
nouveau/nv50: Correct thinko for 8800 chips + cleanup a bit.
2007-08-22 12:54:26 +10:00
Eric Anholt
Dave Airlie
Dave Airlie
Stephane Marchesin
Thomas Hellstrom
Dave Airlie
Kristian Høgsberg
Ben Skeggs
Jeremy Kolb
Pekka Paalanen
Stuart Bennett
Arthur Huillet
Matthieu Castet
Maarten Maathuis
chaohong guo
Jesse Barnes
Michel Dänzer
Ian Romanick
Patrice Mandin
Keith Packard