Commit Graph

6245 Commits (c6fcd176e8949148ad2e07b0ee970cd1ad287113)

Author SHA1 Message Date
Eric Engestrom 76418c244d freedreno/kgsl: fix pointer-to-int cast
Fixes this warning:

freedreno/kgsl/kgsl_ringbuffer.c: In function ‘kgsl_ringbuffer_flush’:
freedreno/kgsl/kgsl_ringbuffer.c:149:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
   req.timestamp = (uint32_t)kgsl_ring->bo->hostptr;
                   ^

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2017-09-15 17:06:29 +01:00
Philipp Zabel 6dca9387d2 etnaviv: prevent deadlock in error path
If drmPrimeFDToHandle fails in etna_bo_from_dmabuf, the function must
not return with the table_lock mutex held. Unlock the mutex in the error
path.

Based on ceb70a6b10 ("freedreno: prevent deadlock in error path").

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-09-14 10:36:07 +01:00
Jan Vesely d55d0804f9 amdgpu: Do not write beyond allocated memory when parsing ids
Fixes crash when/usr/share/libdrm/amdgpu.ids contains ASIC_ID_TABLE_NUM_ENTRIES + 1 entries.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102432
Fixes: 7e6bf88cac (amdgpu: move asic id table to a separate file)
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2017-09-04 23:48:54 -04:00
Alex Deucher 05a830d382 tests/amdgpu: add missing header to SOURCES
Fixes the tarball generation.

fixes: 9d133dd087 (tests/amdgpu: add uvd encode unit tests)
bug: https://bugs.freedesktop.org/show_bug.cgi?id=102391
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-31 10:23:18 -04:00
Daniel Stone f19dbb79fe configure.ac: Bump version to 2.4.83 2017-08-24 12:31:30 +01:00
Philipp Zabel 99d3f8253c etnaviv: fix etna_bo_from_name
Look up BOs from the name table using the name parameter instead of
req.handle (which at this point is always zero).

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2017-08-21 14:04:05 +01:00
Chih-Wei Huang a0531e76f6 android: amdgpu: fix build break
Define two macros to avoid building errors.

Fixes: 7e6bf88cac (amdgpu: move asic id table to a separate file)

Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
2017-08-21 13:05:13 +01:00
Chih-Wei Huang e5ce5c6807 android: add rules to build amdgpu.ids
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
2017-08-21 13:05:13 +01:00
Jan Vesely 20138ea997 drmsltest: Check expected neighbours
Fixes: 7d8c946408
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-21 13:05:13 +01:00
Boyuan Zhang 9d133dd087 tests/amdgpu: add uvd encode unit tests
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-08-16 16:16:50 -04:00
Jason Ekstrand 7ec689a540 drm: Pull new modifier uapi into drm_fourcc and drm_mode
Reviewed-by: Daniel Stone <daniels@collabora.com>
2017-08-15 07:50:46 -07:00
Monk Liu 687d250797 amdgpu: merge and cleanup amdgpu_bo_free
since bo_reference and bo_internal_free are
all only used by bo_free, so we just merge them
together

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-08 12:16:20 -04:00
Monk Liu 2a89ae5d7a amdgpu: fix race issue between two bo functions(v2)
there is race issue between two threads on amdgpu_bo_reference and
amdgpu_bo_import, this patch tends to fix it by moving the
pthread_mutex_lock out of bo_free_internal and move to bo_reference
to cover the update_reference part.

The mutex_unlock in bo_import should also cover bo refcount
increasement.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-08 12:00:11 -04:00
Monk Liu 4d24415594 amdgpu: fix missing mutex unlock before return
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-07 15:00:06 -04:00
Eric Engestrom ceb70a6b10 freedreno: prevent deadlock in error path
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2017-08-07 14:16:41 +01:00
Eric Engestrom 6338e452c9 freedreno/msm: remove dead error path
`ring` cannot be non-null, so the label reduces to a simple return.
Then, there is no point initialising `ring` just to overwrite it before
anyone reads it.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2017-08-07 14:16:41 +01:00
Eric Engestrom ac2b806c45 freedreno: remove dead error path
`pipe` cannot be non-null, so the label reduces to a simple return.
Then, there is no point initialising `pipe` just to overwrite it before
anyone reads it.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2017-08-07 14:16:41 +01:00
Flora Cui e2b6785c5a test/amdgpu: fix test failure for SI
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-04 08:27:06 -04:00
Hawking Zhang 4d0e05eb2a tests/amdgpu: bypass VCE tests on raven
raven doesn't support VCE

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-04 08:25:00 -04:00
Hawking Zhang 517df5f513 tests/amdgpu: bypass UVD CS tests on raven
raven doesn't support UVD decode

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Xiaojie Yuan <Xiaojie.Yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2017-08-04 08:24:51 -04:00
Jan Vesely 0167e6836e amdgpu: Add FX-9800P Bristol Ridge iGPU id
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2017-08-02 11:22:13 -04:00
Eric Engestrom 053ad38487 radeon: add fallthrough annotation
GCC 7 started warning when a switch case has neither a `break` nor
a "fallthrough" comment.
Let's be explicit that we meant to fall through here.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2017-08-01 18:29:28 +01:00
Emil Velikov 3876bc246a xf86drm: continue with next device if drmProcessUsbDevice fails
Analogous to previous commit (and the rest of the codebase), simply
discard the device if we cannot parse it.

Fixes: f8484ccbd1 ("xf86drm: Add USB support")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-20 12:25:27 +01:00
Gurchetan Singh 5226b52773 xf86drm: continue after drmProcessPlatformDevice failure
On ChromeOS devices, readdir() processes the directory in
the following order:

-NAME-              -TYPE-
.                    n/a
..                   n/a
vgem                 n/a
card1           DRM_BUS_PLATFORM
renderD129      DRM_BUS_PLATFORM
card0             DRM_BUS_PCI
renderD128        DRM_BUS_PCI
controlD64        DRM_BUS_PCI

In drmGetDevices2, after drmProcessPlatformDevice fails for
/dev/dri/card1, we don't process the remaining directory entries.
As such, Vulkan fails to initialize since Mesa uses drmGetDevices2.
To fix this, continue if drmProcessPlatformDevice fails.

Fixes: 7b1f37f474 ("xf86drm: Add platform and host1x bus support")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[Emil: correct the host1x platforms as well]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-20 12:23:58 +01:00
Lucas Stach 23e234a350 configure.ac: bump version for release
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2017-07-19 10:49:34 +02:00
Dave Airlie e12af382b5 amdgpu: add new symbols to tests. 2017-07-19 00:40:38 +01:00
Dave Airlie 22790a65d4 drm/amdgpu: add new low overhead command submission API. (v2)
This just sends chunks to the kernel API for a single command
stream.

This should provide a more future proof and extensible API
for command submission.

v2: use amdgpu_bo_list_handle, add two helper functions to
access bo and context internals.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-07-19 00:33:14 +01:00
Dave Airlie 69532d0188 drm/amdgpu: add syncobj create/destroy/import/export apis
These are just wrappers using the amdgpu device handle.

Acked-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-07-19 00:32:53 +01:00
coypu ac21401790 Remove redundant memclear
drmMalloc will zero out the memory for us

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-07-07 10:49:40 +01:00
Christian Gmeiner 2393acd144 etnaviv: submit full struct drm_etnaviv_gem_submit
It is safe to submit the full struct even on older kernels as such
kernels do not process the full struct. Without this change it
becomes quite challenging to extned the submit struct.

Freedreno has no special treatment too. See git commits
- freedreno: sync uapi header
- freedreno: add fence fd support

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-07-06 20:46:27 +02:00
Rodrigo Vivi 68da7812fc intel/intel_chipset: Move IS_9XX below IS_GEN10.
No functional change. Just organizing the code
so it gets clear for future platforms.

Paulo deserves credits becuase he was the one
that just noticed this IS_9XX was in the wrong position
after CNL patches got introduced.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30 14:25:24 -07:00
Paulo Zanoni 3095cc8eab intel: add GEN10 to IS_9XX.
As far as I understand, IS_9XX should return true for it.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30 08:30:48 -07:00
Ben Widawsky 5c490bd685 intel/gen10: Add missed gen10 stuff
This got lost on rebase, I believe

Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-30 08:30:43 -07:00
Rodrigo Vivi 80201d7067 intel: Add Cannonlake PCI IDs for Y-skus.
By the Spec all CNL Y skus are 2+2, i.e. GT2.

This is a copy of merged i915's
commit 95578277cbdb ("drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.")

v2: Add kernel commit id for reference.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
2017-06-30 08:30:28 -07:00
Rodrigo Vivi 6b624bf3c3 intel: Add Cannonlake PCI IDs for U-skus.
Platform enabling and its power-on are organized in different
skus (U x Y x S x H, etc). So instead of organizing it in
GT1 x GT2 x GT3 let's also use the platform sku.

This is a copy of merged i915's
commit e918d79a5d0a ("drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.")

v2: Remove PCI IDs for SKU not mentioned in spec.
v3: Add kernel commit id for reference.

Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
2017-06-30 08:30:08 -07:00
Anusha Srivatsa 4c98652cb5 intel: PCI Ids for U SKU in CFL
Add the PCI IDs for U SKU IN CFL by following the spec.

v2: Update IDs

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29 10:51:29 -07:00
Anusha Srivatsa 2b48faf30e intel: PCI Ids for H SKU in CFL
Add the PCI IDs for H SKU IN CFL by following the spec.

v2: Update IDs

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29 10:51:15 -07:00
Anusha Srivatsa 0733f376ae intel: PCI Ids for S SKU in CFL
Add the PCI IDs for S SKU IN CFL by following the spec.

v2: Update IDs.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2017-06-29 10:50:54 -07:00
Dave Airlie fc4922793f libdrm: add drm syncobj create/destroy/import/export
These ioctls are now in drm next so add the first set of libdrm APIs.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-29 05:32:34 +10:00
Dave Airlie 3832374daf drm: update drm.h to latest in drm-next.
This syncs the drm.h header with my drm-next branch as of
6d61e70ccc21606ffb8a0a03bd3aba24f659502b.

It brings over the semaphore API changes.

Generated using make headers_install.
Generated from git://people.freedesktop.org/~airlied/linux drm-next commit 6d61e70ccc2.

[airlied: I split patch in two, split reviewed by across both]

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-29 05:31:23 +10:00
Dave Airlie 92b5b308ca amdgpu: sync amdgpu_drm with kernel.
This syncs the amdgpu_drm header with my drm-next branch as of
6d61e70ccc21606ffb8a0a03bd3aba24f659502b.

It brings over the VM and semaphore API changes.

Generated using make headers_install.
Generated from git://people.freedesktop.org/~airlied/linux drm-next commit 6d61e70ccc2.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-06-27 13:08:39 +10:00
Eric Anholt b9549c954e headers: Update drm_fourcc and vc4_drm.h with new VC4 tiling UAPI.
Taken from make headers_install of drm-misc-next
(34c8ea400ff6383b028f63df2453914163afc07c)

Reviewed-by: Daniel Stone <daniels@collabora.com>
2017-06-22 10:49:00 +01:00
Xiaojie Yuan 7e6bf88cac amdgpu: move asic id table to a separate file
v2: fix an off by one error and leading white spaces
v3: use thread safe strtok_r(); initialize len before calling getline();
    change printf() to drmMsg(); add initial amdgpu.ids
v4: integrate some recent internal changes, including format changes
v5: fix line number for empty/commented lines; realloc to save memory;
    indentation changes
v6: remove a line error
v7: [Michel Dänzer]
* Move amdgpu.ids to new data directory
* Remove placeholder entries from amdgpu.ids
* Set libdrmdatadir variable in configure.ac instead of Makefile.am
  [Emil Velikov]
* Use isblank() instead of open-coding it [Emil Velikov]
* Don't leak asic_id_table memory if realloc fails [Emil Velikov]
* Check and bump table_max_size at the beginning of the while loop [Emil
  Velikov]
* Initialize table_max_size to the number of entries in data/amdgpu.ids
v8: [Michel Dänzer]
* Make sure amdgpu_asic_id.c gets rebuilt when amdgpu.ids changes

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Samuel Li <Samuel.Li@amd.com>
2017-06-13 10:21:39 +09:00
Michel Dänzer 87dac00db3 amdgpu: Add .editorconfig file for amdgpu coding style
The .editorconfig file in the toplevel directory doesn't match.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2017-06-13 10:20:16 +09:00
Michel Dänzer 57d67d55d3 tests/amdgpu: s/uvd_messages.h/decode_messages.h/ in Makefile.am
Fixes make distcheck with amdgpu enabled.

Fixes: ec65d19809 ("tests/amdgpu: rename uvd messages to decode
                      messages")

Trivial.
2017-06-12 17:16:47 +09:00
Tom St Denis b6f450e065 tests/amdgpu: Fix device_id option
The device_id option [-d] was badly broken.  This commit fixes
the width (was 8 is now 16 bits) as well as enables searches
without specifying a bus id.  It was also comparing "dev" from
the bus field which is not the PCI device id.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
2017-06-06 12:14:13 -04:00
Leo Liu 16444e1061 tests/amdgpu: implement vcn dec unit tests
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-06-05 10:41:13 -04:00
Leo Liu c1f5eea50f tests/amdgpu: add vcn tests support and sets
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-06-05 10:41:13 -04:00
Leo Liu 01096f2122 tests/amdgpu: move decode sum to common
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-06-05 10:41:13 -04:00
Leo Liu 1851f1b57a tests/amdgpu: separate decode messages
AVC decode messages will be common with VCN decode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-06-05 10:41:13 -04:00