Commit Graph

3201 Commits (ce2effbe2dd205e67e294304b97ee7bf221137b1)

Author SHA1 Message Date
Keith Packard 44ed693ca6 [gem] Use CPU domain for new or pageable objects
Newly allocated objects need to be in the CPU domain as they've just been
cleared by the CPU. Also, unmapping objects from the GTT needs to put them
into the CPU domain, both to flush rendering as well as to ensure that any
paging action gets flushed before we remap to the GTT.
2008-05-22 22:00:21 -07:00
Keith Packard 71b09a5f75 [intel-gem] Force ring retire by emiting flush before user-interrupt.
Commands in the ring are parsed and started when the head pointer passes by
them, but they are not necessarily finished until a MI_FLUSH happens. This
patch inserts a flush after the execbuffer (the only place a flush wasn't
already happening).
2008-05-22 22:00:21 -07:00
Keith Packard a51c3a76ff [intel] Add debug code to verify the cached ring tail pointer.
Recording the tail pointer in a local variable improves performance, but if
someone messes up and fails to reload at the right time, the driver will
write commands to the wrong part of the ring and scramble execution badly.

This change (available by setting I915_RING_VALIDATE to 1) checks to make
sure the cached tail pointer matches the hardware tail pointer at each ring
buffer addition, calling BUG_ON when that's not true.
2008-05-22 22:00:21 -07:00
Keith Packard da3f099a7c [intel-gem] invalidate ring locals for pin/unpin/set_domain/free functions
Ring locals must be reloaded from hardware in case the X server ran.
2008-05-22 22:00:21 -07:00
Eric Anholt 5e662f90d1 [gem] Release GEM buffers from work task scheduled from IRQ.
There are now 3 lists.  Active is buffers currently in the ringbuffer.
Flushing is not in the ringbuffer, but needs a flush before unbinding.
Inactive is as before.  This prevents object_free → unbind →
wait_rendering → object_reference and a kernel oops about weird refcounting.

This also avoids an synchronous extra flush and wait when freeing a buffer
which had a write_domain set (such as a temporary rendered to and then from
using the 2d engine).  It will sit around on the flushing list until the
appropriate flush gets emitted, or we need the GTT space for another
operation.
2008-05-22 22:00:21 -07:00
Dave Airlie 49075b678f r500: add two more register ranges for mesa driver to setup 2008-05-23 09:40:26 +10:00
Dave Airlie 74a9ea896e drm: fix nouveau warning 2008-05-23 09:40:26 +10:00
Eric Anholt d6f7968577 [gem] Replace ring throttling hack with actual time measurement. 2008-05-21 16:40:14 -07:00
Eric Anholt 54fa32cdfe [gem] Fix bad test for list_for_each completion.
Since it's a circular list, the entry won't be NULL at termination.
2008-05-21 15:15:58 -07:00
Eric Anholt 7078978db0 [gem] Hold a reference on the object in i915_gem_wait_space.
Otherwise, in the middle of the function called using it the last ref
might disappear.
2008-05-21 15:04:07 -07:00
Keith Packard f8e38e49dd [intel-gem] invalidate ring locals for pin/unpin/set_domain/free functions
Ring locals must be reloaded from hardware in case the X server ran.
2008-05-21 15:00:16 -07:00
Dave Airlie 91c6c4b240 rs690/r500: vblank support.
The new display controller has the vblank interrupts in a different place.

Add support for vbl interrupts for these chips
2008-05-21 21:27:33 +10:00
Eric Anholt af8e087157 [gem] Use a separate sequence number field from classic/ttm
This lets us get some qualities we desire, such as using the full 32-bit
range (except zero), avoiding DRM_WAIT_ON, and a 1:1 mapping of active
sequence numbers to request structs, which will be used soon for throttling
and interrupt-driven list cleanup.
2008-05-20 14:16:26 -07:00
Eric Anholt ab36a6f983 [gem] Rename sequence numbers from "cookie" to "seqno" 2008-05-20 10:53:10 -07:00
Eric Anholt 6c3ac484b0 [gem] Clean up active/inactive list handling using helper functions.
Additionally, a boolean active field is added to indicate which list an
object is on, rather than smashing last_rendering_cookie to 0 to show
inactive.  This will help with flush-reduction later on, and makes the code
clearer.
2008-05-20 10:52:39 -07:00
Dave Airlie 8399656106 r500: add more register ranges for Mesa driver 2008-05-17 10:22:12 +10:00
Eric Anholt 7dced2f33a [gem] Hold dev->struct_mutex to protect structure data. 2008-05-15 18:45:23 -07:00
Eric Anholt 3ab152da66 [gem] Rename the GTT LRU lists to active (executing) and inactive (idle). 2008-05-15 11:59:58 -07:00
Eric Anholt aafafe507b [gem] typo fix in comment. 2008-05-15 11:59:57 -07:00
Dave Airlie a09c0bbe11 ati_pcigart: oops wrong way around not that it actually mattered 2008-05-14 22:48:12 +10:00
Dave Airlie 4c6ec02eb8 ati_pcigart: stop working in the evenings you mess up too often 2008-05-14 22:44:22 +10:00
Dave Airlie 2712cdeec3 Revert "ati_pcigart: fixup properly this version might even work"
This reverts commit bc0836e12a.

tree has some kref hacks in it - oops
2008-05-14 22:43:28 +10:00
Dave Airlie bc0836e12a ati_pcigart: fixup properly this version might even work 2008-05-14 22:42:21 +10:00
Dave Airlie dd1f33f83c ati_pcigart: fill out 40-bit gart table support properly
Thanks to Alex for supplying this info.
2008-05-14 22:35:32 +10:00
Alex Deucher caace3692f RS4xx: separate out RS400 and RS480 IGP chips
RS400 (intel based IGP) and RS480 (AMD based IGP) have
different MC and GART setups.  Currently we only support
RS480.
2008-05-13 21:02:17 -04:00
Eric Anholt 6e46a3c762 [GEM] Update testcases for new API. 2008-05-12 15:42:20 -07:00
Eric Anholt f650d7240a [GEM] Typo (and thinking) fixes in drm-gem.txt and doxygen. 2008-05-12 13:17:01 -07:00
Keith Packard 17e8000ac0 [intel] Minor kludge -- wait for the ring to be nearly empty before queuing
No need to fill the ring that much; wait for it to become nearly empty
before adding the execbuffer request. A better fix will involve scheduling
ring insertion in the irq handler.
2008-05-12 13:04:18 -07:00
Keith Packard 7e7ea313c4 [intel] When polling for ring space, sleep for a lot longer (10ms)
If the ring is full, the engine will surely be running for more than 10ms.
2008-05-12 13:03:16 -07:00
Keith Packard 6aeff6b9e3 [gem] Set write domain to CPU when doing pwrite.
Leave the flush call in place, which can fix domains up if necessary.
2008-05-12 13:01:57 -07:00
Keith Packard 6950b7da71 [gem] Clarify use of explicit domain control. Remove Gen3 from I-cache usage. 2008-05-12 13:00:55 -07:00
Alex Deucher 10d754f0a2 RADEON: fix copy/pasto in last commit 2008-05-12 14:49:43 -04:00
Alex Deucher 75bc739bee R3/4/5: init pipe setup in drm
Similar (broken) code in mesa needs to be removed
2008-05-12 09:44:20 -04:00
Alex Deucher e16a7101e8 RADEON: cleanup radeon_do_engine_reset() 2008-05-12 09:35:06 -04:00
Alex Deucher 5532b8d2a0 R300+: fixup pixcache flush 2008-05-12 09:30:47 -04:00
Alex Deucher 3582e82f14 RS4xx: fix MCIND index mask 2008-05-12 09:24:13 -04:00
Alex Deucher d26af273f8 RADEON: write AGP_BASE_2 on chips that support it 2008-05-12 09:21:45 -04:00
Alex Deucher c307e50724 R300+: fixup PURGE/FLUSH macros 2008-05-12 09:18:28 -04:00
Alex Deucher fb9eaff747 Radeon IGP: merge RS4xx/RS6xx gart setup 2008-05-12 09:13:44 -04:00
Alex Deucher 68b7f550ba Radeon IGP: wrap MCIND access
first step in merging rs4xx/rs6xx gart setup
2008-05-12 09:00:40 -04:00
Alex Deucher a34025ce22 Radeon IGP: clean up registers and magic numbers 2008-05-12 08:56:11 -04:00
Keith Packard ff39db099b [GEM] Make pread/pwrite manage memory domains. No luck with movnti though.
pread and pwrite must update the memory domains to ensure consistency with
the GPU. At some point, it should be possible to avoid clflush through this
path, but that isn't working for me.
2008-05-11 00:10:16 -07:00
Keith Packard 1b0bf30143 [intel-GEM] exec list can contain pinned, lru cannot.
The exec list contains all objects, in order of use. The lru list contains
only unpinned objects ready to be evicted. This required two changes -- the
first was to not migrate pinned objects from exec to lru, the second was to
search for the first unpinned object in the exec list when doing eviction.
2008-05-10 22:04:39 -07:00
Keith Packard 1f9eaceb71 Merge commit 'anholt/drm-gem' into drm-gem 2008-05-10 21:05:25 -07:00
Keith Packard 177b8b0703 [GEM] Add drm-gem.txt
Add some API and implementation documentation for GEM.
2008-05-10 21:04:42 -07:00
Keith Packard a37ac493da [intel-GEM] Clean up GEM ioctl naming.
Rename 'validate_entry' to 'exec_object', then clean up some field names in
structures (renaming buffer_offset to just offset, for example).
2008-05-10 21:04:18 -07:00
Eric Anholt 48a8531aa4 GEM: Fix arguments to drm_memrange_init so we don't exceed our allocation.
It takes (offset, size), not (offset, end).
2008-05-09 18:23:51 -07:00
Eric Anholt c5c59eab80 GEM: Separate the LRU into execution list and LRU list.
Now, the LRU list has objects that are completely done rendering and ready
to kick out, while the execution list has things with active rendering,
which have associated cookies and reference counts on them.
2008-05-09 17:38:32 -07:00
Eric Anholt f56f2acb5a GEM: Clear obj_priv->agp_mem when we free it.
Still managing to get something wrong with this, oopsing down in agp.
2008-05-09 15:07:49 -07:00
Eric Anholt f0ae335cd7 GEM: Avoid leaking refs on target objects on presumed offset success. 2008-05-09 15:02:50 -07:00