3f70518f0b
drm/bo: avoid oops if the memory manager for this type isn't initialised
2007-03-29 09:25:04 +10:00
bdabc8f998
nouveau: fix nv04 context switches.
2007-03-29 00:54:18 +02:00
81b811da37
drm/i915: set the bo up at firstopen time not after DMA init
...
This is required to use TTM to allocate the ring buffer.
2007-03-27 18:01:31 +10:00
72a1190f6d
drm/ttm: make sure dev_mapping is set-up for the first opener of the drm
...
This was causing an oops in my miniglx code to try and use a TTM-only setup.
2007-03-27 17:59:30 +10:00
406a894e52
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-27 12:53:13 +08:00
674cefd4fe
nouveau: move card initialisation into the drm
...
The PGRAPH init for the various cards will need cleaning up at some point,
a lot of the values written there are per-context state left over from the
all the hardcoding done in the ddx.
It's possible some cards get broken by this commit, let me know.
Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 20:59:37 +10:00
ddc87d3025
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-25 17:00:36 +08:00
5d69640a6a
Catch up to new interrupt API, and retire FreeBSD 4.x support here.
2007-03-24 09:39:09 -07:00
5ad43f4675
vm: cleanup drm_vm.c along lines of cleanups queued for kernel
2007-03-24 17:58:27 +11:00
e7cd5a1e2d
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-23 17:00:41 +08:00
4988fa4886
nouveau: rework nouveau_fifo_alloc() so the drm can create internal FIFOs
2007-03-23 15:25:37 +11:00
8d918b0b63
cleanup more whitespace from ttm merge
2007-03-23 14:56:39 +11:00
39795501a8
drm: remove second spinlock init for tasklet lock
2007-03-23 14:56:28 +11:00
2bb9de96d5
nouveau: remove unused cruft
2007-03-23 13:45:29 +11:00
0467ad4118
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-21 17:00:43 +08:00
e22225416a
nouveau: support multiple channels per client (breaks drm interface)
2007-03-21 17:57:47 +11:00
fe4cc50983
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-20 13:11:02 +08:00
209870a882
rename badly named define
2007-03-20 10:13:58 +11:00
ef71b6230b
remove i830 reference
2007-03-19 11:46:35 +00:00
cbe31d0dc7
Remove old i830 kernel driver.
2007-03-19 11:46:35 +00:00
8398b99d8d
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-19 17:00:31 +08:00
1e77e52755
more return values fixup
2007-03-19 09:20:04 +11:00
46fac17082
fixup return values in drm ioctl
2007-03-19 09:12:08 +11:00
26aba875e1
more whitespace issues
2007-03-19 08:56:24 +11:00
c991f8e049
cleanup ioctl expansion code
2007-03-19 08:46:39 +11:00
a2e3bae8e2
oops missing else
2007-03-19 08:46:25 +11:00
bbb6fc9307
make drm fops const from kernel
2007-03-19 08:36:01 +11:00
483f6a113d
use ARRAY_SIZE
2007-03-19 08:32:25 +11:00
2d7ecb8422
more tab/space conversion
2007-03-19 08:29:07 +11:00
2463b03cb4
whitespace cleanup pending a kernel merge
2007-03-19 08:23:43 +11:00
6c4428d40c
clean up more of inline functions agp_remap/drm_lookup_map
2007-03-19 08:09:21 +11:00
27197d7836
deinline agp_remap along lines of kernel
2007-03-18 21:45:07 +11:00
c4808e206b
remove drm_lookup_map unused now
2007-03-18 21:42:48 +11:00
df73975980
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-14 17:00:27 +08:00
93f66af76a
r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; not
...
enough information is known about them to be sure as to what the values mean.
2007-03-13 14:48:01 +00:00
80d0018bc0
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-13 17:00:31 +08:00
a90c2854a7
Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.
...
Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these
values are really unknown; ideally more reverse engineering should be done to
determine what these values mean and when they should be set.
2007-03-13 06:25:04 +00:00
90f8c691a5
nouveau: make sure cmdbuf object gets destroyed
2007-03-13 14:55:54 +11:00
1775202cf9
nouveau: associate all created objects with a channel + cleanups
2007-03-13 14:55:54 +11:00
7e2bbe2954
nouveau: s/fifo/channel/
2007-03-13 14:55:54 +11:00
462a6ea4ca
Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to either
...
R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values.
2007-03-13 01:19:56 +00:00
5667396e05
Guess another unknown register used for R300 pacification.
2007-03-13 00:50:05 +00:00
ab75d50d6c
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-12 09:03:40 +08:00
0cd5c650d1
nouveau: PUT,GET, not 2xPUT
2007-03-11 14:02:40 +01:00
b369724077
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-07 16:01:50 -05:00
6ffe94f008
Add via CX700.
2007-03-07 09:19:57 +01:00
0a85c9fa02
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-05 09:01:45 -05:00
188a93c9df
radeon: make PCI GART aperture size variable, but making table size variable
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This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0
2007-03-04 19:10:46 +11:00
c9178c3d01
ati: make pcigart code able to handle variable size PCI GART aperture
...
This code doesn't enable a variable aperture it just modifies the codebase
to allow me fix it up later
2007-03-04 18:16:29 +11:00
6c48b8e7ff
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-01 09:02:09 -05:00
Dave Airlie
Stephane Marchesin
Nian Wu
Ben Skeggs
Eric Anholt
Alan Hourihane
Oliver McFadden
Patrice Mandin
Thomas Hellstrom