893cd01a1d
i915: register definition & header file cleanup
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It would be nice if one day the DRM driver was the canonical source for
register definitions and core macros. To that end, this patch cleans things up
quite a bit, removing redundant definitions (some with different names
referring to the same register) and generally tidying up the header file.
2008-06-24 12:51:29 -07:00
01e8f0ea42
nv50: oops, keep VRAM allocations aligned at 64KiB - that's our page size..
2008-06-23 02:42:15 +10:00
89cf2ee2e5
nv50: use same dma object for fb/tt access
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We depend on the VM fully now for memory protection, separate DMA objects
for VRAM and GART are unneccesary. However, until the next interface break
(soon) a client can't depend on the objects being the same and must still
call NV_OBJ_SET_DMA_* methods appropriately.
2008-06-23 01:24:11 +10:00
b9ed0f9950
nouveau: allocate drm-use vram buffers from end of vram.
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This avoids seeing garbage from engine setup etc before X gets around
to pointing the CRTCs at a new scanout buffer. Not actually a noticable
problem before G80 as PRAMIN is forced to the end of VRAM by the hardware
already.
2008-06-23 01:00:42 +10:00
207f701e1a
RADEON: 0x1002 0x5657 is actually an RV410
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See bug 14289
2008-06-21 10:46:55 -04:00
9d79944a93
r300: fix warning
2008-06-20 15:35:16 +10:00
00f549bd5f
i915: Add support for Intel 4 series chipsets
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Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
2008-06-18 14:19:38 +08:00
59112c9e52
radeon: *really* fix screen corruption thanks to Lukasz Krotowski
2008-06-15 20:18:29 +02:00
6f8cc95703
radeon: actualy try to fix the corruption
2008-06-15 19:31:02 +02:00
9dd58d6568
radeon: fix screen corruption introduced by last patch
2008-06-15 18:49:47 +02:00
00b4063906
radeon: bump driver date to know if lockup fix is in
2008-06-13 10:02:41 +02:00
1aafbb83d9
radeon: r345xx fixe hard lockup
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This patch should fixe hard lockup and convert them in
softlockup (ie you can ssh the box but the gpu is busted
and we are waiting in loop for it to come back to reason).
2008-06-13 09:54:05 +02:00
a07c82183a
RADEON: use DSTCACHE_CTLSTAT rather than RB2D_DSTCACHE_CTLSTAT
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According to the hw guys, you should use DSTCACHE_CTLSTAT to flush
the 2D dst cache rather than RB2D_DSTCACHE_CTLSTAT.
2008-06-11 18:25:47 -04:00
b535567ee9
xgixp: Remove dependency on TTM fences
2008-06-10 22:18:14 -07:00
4b8aecbde8
RADEON: Add untested support for RS400 chips
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GART setup appears to work the same as RS480 chips.
Also RC4xx chips are actually RS400 based, not RS480 based.
2008-06-09 16:58:06 -04:00
f6982b54c9
RADEON: switch IGP gart to use radeon_write_agp_base()
2008-06-09 16:28:35 -04:00
63eb58040d
Fix typo in i915_suspend
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Reported by vehemens
2008-06-08 23:46:14 -04:00
116870a908
I915 suspend/resume for FreeBSD
2008-06-08 13:56:14 -04:00
d43f3cb097
r300/r500: add hier-z regs
2008-06-09 05:32:41 +10:00
6905c7a29d
radeon: Restore software interrupt on resume.
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Fixes performance drop after suspend/resume on some systems.
2008-06-05 18:23:37 +02:00
d5ae19ebcf
drm: sg alloc should write back the handle to userspace
2008-06-03 12:44:06 +10:00
a12cbf8aa5
RADEON: fix typo in last commit
2008-05-30 18:20:01 -04:00
6e8a2cff66
r500: attempt to make AGP work by programming agp base in the MC correctly
2008-05-30 20:27:31 +10:00
5b86823fa3
radeon: split microcode out into a separate header file.
2008-05-28 11:12:57 +10:00
0c8a8db1b6
i915: fix BSD bh, DRI2 not uses anywhere else
2008-05-28 10:28:13 +10:00
c06096d34f
radeon: bump release date/version for r500 3D support
2008-05-28 10:02:20 +10:00
59c953245c
RADEON: add get_param for number of GB pipes
2008-05-27 18:34:33 -04:00
e45f95a03b
[i915] Fix typo in (unused) START_ADDR definition.
2008-05-27 14:55:01 -07:00
8cd045079e
[FreeBSD] Add vblank-rework support and get drivers building.
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The i915 driver now works again.
2008-05-27 14:25:20 -07:00
49075b678f
r500: add two more register ranges for mesa driver to setup
2008-05-23 09:40:26 +10:00
74a9ea896e
drm: fix nouveau warning
2008-05-23 09:40:26 +10:00
91c6c4b240
rs690/r500: vblank support.
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The new display controller has the vblank interrupts in a different place.
Add support for vbl interrupts for these chips
2008-05-21 21:27:33 +10:00
8399656106
r500: add more register ranges for Mesa driver
2008-05-17 10:22:12 +10:00
caace3692f
RS4xx: separate out RS400 and RS480 IGP chips
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RS400 (intel based IGP) and RS480 (AMD based IGP) have
different MC and GART setups. Currently we only support
RS480.
2008-05-13 21:02:17 -04:00
10d754f0a2
RADEON: fix copy/pasto in last commit
2008-05-12 14:49:43 -04:00
75bc739bee
R3/4/5: init pipe setup in drm
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Similar (broken) code in mesa needs to be removed
2008-05-12 09:44:20 -04:00
e16a7101e8
RADEON: cleanup radeon_do_engine_reset()
2008-05-12 09:35:06 -04:00
5532b8d2a0
R300+: fixup pixcache flush
2008-05-12 09:30:47 -04:00
3582e82f14
RS4xx: fix MCIND index mask
2008-05-12 09:24:13 -04:00
d26af273f8
RADEON: write AGP_BASE_2 on chips that support it
2008-05-12 09:21:45 -04:00
c307e50724
R300+: fixup PURGE/FLUSH macros
2008-05-12 09:18:28 -04:00
fb9eaff747
Radeon IGP: merge RS4xx/RS6xx gart setup
2008-05-12 09:13:44 -04:00
68b7f550ba
Radeon IGP: wrap MCIND access
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first step in merging rs4xx/rs6xx gart setup
2008-05-12 09:00:40 -04:00
a34025ce22
Radeon IGP: clean up registers and magic numbers
2008-05-12 08:56:11 -04:00
d015219bd0
r500: add allowed range for us config/pixsize
2008-05-05 17:03:27 +10:00
3ac74f3208
nv50: enable 0x400500 bit 0 after PGRAPH exception also
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No solid idea about what these 2 bits do, but nv50 can now survive a few
PGRAPH exceptions just as nv40 does :)
2008-05-02 01:36:30 +10:00
6d8062ac1e
nouveau: guard against channels potentially not having a context, fix nv50
2008-05-02 01:36:08 +10:00
77d20928b3
nouveau: disable all card interrupts when unknown PFIFO IRQ occurs.
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This is possibly temporary. I can trigger an unending IRQ storm on G8x
in some circumstances, and have no idea how to handle that particular PFIFO
exception correctly yet.
2008-05-02 00:53:42 +10:00
5c4c778c0d
nouveau: restore original NV_PFIFO_CACHES_REASSIGN value in fifo handler
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Doesn't fix any issue I've seen, but is a potential issue if a FIFO IRQ
occurs during channel creation/takedown.
2008-05-02 00:52:21 +10:00
bfbe4ade32
nouveau: gather nsource in trap_info()
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The IRQ handling stuff really is a mess.. On the TODO :)
2008-05-02 00:51:00 +10:00
Jesse Barnes
Ben Skeggs
Ben Skeggs
Alex Deucher
Dave Airlie
Zhenyu Wang
Jerome Glisse
Alex Deucher
Ian Romanick
Robert Noland
Dave Airlie
Dennis Kasprzyk
Jie Luo
Robert Noland
Alex Deucher