Ben Skeggs
4f2dd78ff3
nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaks
2007-06-28 03:04:48 +10:00
Thomas Hellstrom
9b9a127ed0
More 64-bit padding.
2007-06-26 23:25:40 +02:00
Ian Romanick
8cee7dca95
Clean up warnings about unused variables and functions.
2007-06-26 13:46:36 -07:00
Ian Romanick
b9ef1467fe
Clean up mixed declarations and code.
2007-06-26 13:39:01 -07:00
Ian Romanick
3547fbda63
Revert over-zealous change from previous commit.
2007-06-26 13:29:28 -07:00
Ian Romanick
3a776fa01e
Add XGI driver to Makefiles.
2007-06-26 13:26:10 -07:00
Ian Romanick
47bf6239aa
Clean up compile-time kernel feature detection.
2007-06-26 13:20:15 -07:00
Ian Romanick
7a053306a9
linux/config.h is deprecated or gone.
2007-06-26 13:16:04 -07:00
Ian Romanick
ec9e494eb9
Gut support for pre-2.6 kernels.
2007-06-26 13:15:22 -07:00
Ian Romanick
434657a258
dos2unix and Lindent
2007-06-26 13:10:30 -07:00
Ian Romanick
7af9d67037
Initial XP10 code drop from XGI.
...
See attachment 10246 on https://bugs.freedesktop.org/show_bug.cgi?id=5921
2007-06-26 13:05:29 -07:00
Ian Romanick
5c27f8a70e
Add support SiS based XGI chips to SiS DRM.
2007-06-26 09:51:55 -07:00
Ben Skeggs
9f617522d9
nouveau: NV49/NV4B PGRAPH setup from jb17bsome and stephan_2303
2007-06-25 01:57:57 +10:00
Ben Skeggs
3dfc13e2da
nouveau: kill some dead code
2007-06-24 19:00:44 +10:00
Ben Skeggs
5f05cd7086
nouveau: NV04/NV10/NV20 PGRAPH engtab functions
...
NV04/NV10 load_context()/save_context() are stubs. I don't know enough about
how they work to implement them sanely. The "old" context_switch() code
remains hooked up, so it shouldn't break anything.
NV20 will probably break if load_context() works. No inital context values
are filled in, so when the first channel is created PGRAPH will probably end
up having its state zeroed. Some setup from nv20_graph_init() will probably
need to be moved to the per-channel context setup.
2007-06-24 19:00:26 +10:00
Ben Skeggs
5d55b0655c
nouveau: NV3X PGRAPH engtab functions
2007-06-24 18:58:38 +10:00
Ben Skeggs
341bc78207
nouveau: NV1X/2X/3X PFIFO engtab functions
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Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC
entry size.
2007-06-24 18:58:14 +10:00
Ben Skeggs
05d86d950a
nouveau: NV04 PFIFO engtab functions
2007-06-24 18:57:09 +10:00
Ben Skeggs
acb710d1a5
nouveau: NV4X PGRAPH engtab functions
2007-06-24 18:56:40 +10:00
Ben Skeggs
f2e64d5276
nouveau: NV4X PFIFO engtab functions
2007-06-24 18:56:01 +10:00
Ben Skeggs
0afb3b518e
nouveau: split PFIFO/PGRAPH context creation
2007-06-24 18:55:23 +10:00
Ben Skeggs
9dbf322d26
nouveau: (mostly) hook up put_base again
2007-06-24 18:55:06 +10:00
Ben Skeggs
24b71c318a
nouveau: prototype PFIFO/PGRAPH engtab API
2007-06-24 18:54:51 +10:00
Ben Skeggs
5c7c07fd49
nouveau: rename engtab functions
2007-06-24 18:54:36 +10:00
Michel Dänzer
068ffc1e1b
radeon: Acknowledge all interrupts we're interested in.
...
Failure to do so was probably the root cause of fd.o bug 11287.
2007-06-22 11:55:26 +02:00
Oliver McFadden
40f6a696cb
r300: Synchronized the register defines file; documentation changes.
2007-06-21 14:35:11 +00:00
Oliver McFadden
213732af43
r300: Allow writes to R300_VAP_PVS_WAITIDLE.
2007-06-21 14:32:58 +00:00
Oliver McFadden
215787e429
r300: Registers 0x2220-0x2230 are known as R300_VAP_CLIP_X_0-R300_VAP_CLIP_Y_1.
2007-06-18 08:42:46 +00:00
Oliver McFadden
8038e7b60f
r300: Synchronized the register defines file again.
2007-06-18 08:36:50 +00:00
David Woodhouse
638ebbab54
fix radeon setparam on 32/64 systems, harder.
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Commit 9b01bd5b284bbf519b726b39f1352023cb5e9e69 introduced a
compat_ioctl handler for RADEON_SETPARAM, the sole purpose of which was
to handle the fact that on i386, alignof(uint64_t)==4.
Unfortunately, this handler was installed for _all_ 64-bit
architectures, instead of only x86_64 and ia64. And thus it breaks
32-bit compatibility on every other arch, where 64-bit integers are
aligned to 8 bytes in 32-bit mode just the same as in 64-bit mode.
Arnd has a cunning plan to use 'compat_u64' with appropriate alignment
attributes according to the 32-bit ABI, but for now let's just make the
compat_radeon_cp_setparam routine entirely disappear on 64-bit machines
whose 32-bit compat support isn't for i386. It would be a no-op with
compat_u64 anyway.
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2007-06-18 12:46:00 +10:00
Michel Dänzer
3d5d41fa98
i915: Fix handling of breadcrumb counter wraparounds.
2007-06-15 17:13:11 +02:00
Thomas Hellstrom
84bea38353
Fix i915 sequence mask.
2007-06-15 10:35:52 +02:00
Thomas Hellstrom
3ee31a1f35
Indentation fixes.
2007-06-15 10:31:32 +02:00
Thomas Hellstrom
d34b2c7b9e
Fix refcounting / lock race.
...
Reported by Steve Wilkins / Michel Dnzer.
2007-06-15 10:26:51 +02:00
Thomas Hellstrom
e1b8eabeee
Locking fixes and instrumentation.
2007-06-15 10:26:51 +02:00
Thomas Hellstrom
2407ce57de
Fix drmMMUnlock / drmMMLock return values.
2007-06-13 15:59:28 +02:00
Thomas Hellstrom
62082ab3e6
Make sure we read fence->signaled while spinlocked.
2007-06-13 15:38:59 +02:00
Thomas Hellstrom
5156f1c897
Fix fence object deref race.
2007-06-13 15:19:30 +02:00
Thomas Hellstrom
f984b1b8d1
Fix some obvious bugs.
2007-06-12 12:30:33 +02:00
Thomas Hellstrom
b6b5df24b9
Try to make buffer object / fence object ioctl args 64-bit safe.
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Introduce tile members for future tiled buffer support.
Allow user-space to explicitly define a fence-class.
Remove the implicit fence-class mechanism.
64-bit wide buffer object flag member.
2007-06-12 12:21:38 +02:00
Dave Airlie
280083d4a2
use krh's idr mods to remove lists from idr code
2007-06-10 15:40:21 +10:00
Oliver McFadden
3181573073
r300: Added the CP maximum fetch size and ring rptr update variables.
2007-06-08 19:40:57 +00:00
Dave Airlie
7426da7538
oops must fix this properly at some point
2007-06-07 18:45:00 +10:00
Dave Airlie
e22f428f5f
drm: fix radeon setparam alignment issues on 32/64-bit
2007-06-07 18:41:18 +10:00
Dave Airlie
abf35cbdcf
radeon: PCIGART memory is Can't map aperture as well there is one
...
on the CPU.... with this my indirect buffers at least start to live..
(cherry picked from commit 699cd9fc6c3794856f7e602088c77d0dfc11a122)
2007-06-07 15:37:03 +10:00
Oliver McFadden
39625f9621
r300: Small correction to the previous commit.
2007-06-05 19:19:42 +00:00
Alex Deucher
9e0bd88c61
r300: Document more of the RADEON_RBBM_STATUS register.
2007-06-05 19:05:49 +00:00
Wang Zhenyu
109e2a10f2
Add support for the G33, Q33, and Q35 chipsets.
...
These require that the status page be referenced by a pointer in GTT, rather
than phsyical memory. So, we have the X Server allocate that memory and tell
us the address, instead.
2007-06-05 11:15:29 -07:00
Dave Airlie
03ce98aa28
set start to gart_vm_start at least
2007-06-05 18:23:24 +10:00
Dave Airlie
96705ce664
add wbinvd calls
2007-06-05 18:23:05 +10:00