feb6803778
move i915 to new drm_wait_on function
2007-04-28 15:07:43 +10:00
9f9c19065c
remove DRM_GETSAREA and replace with drm_getsarea function
2007-04-28 15:07:43 +10:00
e88934274a
Revert "bug 7092 : add pci ids for mach64 in Dell poweredge 4200"
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This reverts commit 255f3e6f76
2007-04-26 14:16:51 +03:00
942d9be296
freebsd: remove stray apperance of IN_MODULE.
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The xserver no longer uses the libc-wrapper.
2007-04-26 14:16:13 +03:00
3c384a9ad5
Add new buffer object type for kernel allocations that don't initially have a user mapping.
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(cherry picked from commit 2e21779992
2007-04-26 16:04:09 +10:00
61477d60c4
nouveau: fix wacky pci id
2007-04-23 22:37:36 +02:00
e805ca959d
via: Make sure we flush write-combining using a follow-up read.
2007-04-17 08:58:23 +02:00
9b7211dd67
nouveau: nv10 per channel init from ddx
2007-04-10 23:20:13 +02:00
059b5d9077
rs480: Renamed some unknown registers. See dri-devel list.
2007-04-09 23:23:40 +00:00
2d7f9f59c3
nouveau: NV46 support
2007-04-09 23:20:26 +10:00
29f8fe8046
radeon: bump version for IGPGART support
2007-04-09 22:00:34 +10:00
a70f8e0ab2
radeon: add support for reverse engineered xpress200m
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The IGPGART setup code was traced using mmio-trace on fglrx by myself
and Phillip Ezolt <phillipezolt@gmail.com> on dri-devel.
This code doesn't let the 3D driver work properly as the card has no
vertex shader support.
Thanks to Matthew Garrett + Ubuntu for providing me some hardware to do this
work on.
2007-04-09 21:52:59 +10:00
46257c51c1
i915: use breadcrumb macro everywhere
2007-04-06 20:21:44 +10:00
78034c06df
nouveau: make a note about a bit that breaks some cards
2007-04-06 03:27:55 +10:00
38f52402a8
nouveau: Power up all card units by default on startup.
2007-04-06 03:26:19 +10:00
139e4bbc73
Make sure we ack irqs before we read a breadcrumb so that
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breadcrumb updates that occur _AFTER_ we've read the breadcrumb really
generates a new IRQ.
2007-04-03 10:29:15 +02:00
5395a92d40
r300: Synchronize the register header file again.
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It's a good idea to keep these synchronized; even though the DRM doesn't use all
the defines, maintaining two different copies is prone to errors when the diff
gets bigger.
2007-04-02 19:45:10 +00:00
cbbdbd5e65
nouveau: fix usage of PGRAPH_CTX_CONTROL on nv20+
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http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=17985f07d68322519919a7f629a6d2d9bf3916ed could have broken some nvxx_graph code : it rename NV03_PGRAPH_CTX_CONTROL to NV10_PGRAPH_CTX_CONTROL, but forgot to update it in nvxx_graph file.
Also when migrating init stuff in http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=674cefd4fe4b537a20a10edcb4ec5df55facca8e , NV04_PGRAPH_CTX_CONTROL is used everywhere but the old ddx code use NV_PGRAPH_CTX_CONTROL_NV04 or NV_PGRAPH_CTX_CONTROL.
2007-04-01 14:31:41 +02:00
25cedcf76f
nouveau : nv10 ctx switch fix
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restoring NV10_PGRAPH_CTX_SWITCH1 now works
2007-04-01 14:21:29 +02:00
223061e084
nouveau : set the correct PGRAPH_CTX_CONTROL register
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"5a072f32 (Stephane Marchesin 2007-02-03 04:57:06 +0100" broke nv10 ctx switch by setting wrong PGRAPH_CTX_CONTROL reg
2007-04-01 00:44:11 +02:00
ddb1715e06
Merge branch 'crestline-qa', adding support for the 965GM chipset.
2007-03-30 13:11:39 -07:00
bdabc8f998
nouveau: fix nv04 context switches.
2007-03-29 00:54:18 +02:00
81b811da37
drm/i915: set the bo up at firstopen time not after DMA init
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This is required to use TTM to allocate the ring buffer.
2007-03-27 18:01:31 +10:00
406a894e52
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-27 12:53:13 +08:00
674cefd4fe
nouveau: move card initialisation into the drm
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The PGRAPH init for the various cards will need cleaning up at some point,
a lot of the values written there are per-context state left over from the
all the hardcoding done in the ddx.
It's possible some cards get broken by this commit, let me know.
Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 20:59:37 +10:00
e7cd5a1e2d
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-23 17:00:41 +08:00
4988fa4886
nouveau: rework nouveau_fifo_alloc() so the drm can create internal FIFOs
2007-03-23 15:25:37 +11:00
2bb9de96d5
nouveau: remove unused cruft
2007-03-23 13:45:29 +11:00
0467ad4118
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-21 17:00:43 +08:00
e22225416a
nouveau: support multiple channels per client (breaks drm interface)
2007-03-21 17:57:47 +11:00
8398b99d8d
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-19 17:00:31 +08:00
26aba875e1
more whitespace issues
2007-03-19 08:56:24 +11:00
2463b03cb4
whitespace cleanup pending a kernel merge
2007-03-19 08:23:43 +11:00
df73975980
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-14 17:00:27 +08:00
93f66af76a
r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; not
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enough information is known about them to be sure as to what the values mean.
2007-03-13 14:48:01 +00:00
80d0018bc0
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-13 17:00:31 +08:00
a90c2854a7
Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.
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Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these
values are really unknown; ideally more reverse engineering should be done to
determine what these values mean and when they should be set.
2007-03-13 06:25:04 +00:00
90f8c691a5
nouveau: make sure cmdbuf object gets destroyed
2007-03-13 14:55:54 +11:00
1775202cf9
nouveau: associate all created objects with a channel + cleanups
2007-03-13 14:55:54 +11:00
7e2bbe2954
nouveau: s/fifo/channel/
2007-03-13 14:55:54 +11:00
462a6ea4ca
Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to either
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R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values.
2007-03-13 01:19:56 +00:00
5667396e05
Guess another unknown register used for R300 pacification.
2007-03-13 00:50:05 +00:00
ab75d50d6c
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-12 09:03:40 +08:00
0cd5c650d1
nouveau: PUT,GET, not 2xPUT
2007-03-11 14:02:40 +01:00
b369724077
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-07 16:01:50 -05:00
6ffe94f008
Add via CX700.
2007-03-07 09:19:57 +01:00
0a85c9fa02
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-05 09:01:45 -05:00
188a93c9df
radeon: make PCI GART aperture size variable, but making table size variable
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This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0
2007-03-04 19:10:46 +11:00
c9178c3d01
ati: make pcigart code able to handle variable size PCI GART aperture
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This code doesn't enable a variable aperture it just modifies the codebase
to allow me fix it up later
2007-03-04 18:16:29 +11:00
6c48b8e7ff
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-01 09:02:09 -05:00
Dave Airlie
George Sapountzis
Jesse Barnes
Stephane Marchesin
Thomas Hellstrom
Matthieu Castet
Oliver McFadden
Ben Skeggs
Eric Anholt
Nian Wu
Patrice Mandin