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drm/shared-core/nouveau_drv.h

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initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
/*
* Copyright 2005 Stephane Marchesin.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __NOUVEAU_DRV_H__
#define __NOUVEAU_DRV_H__
#define DRIVER_AUTHOR "Stephane Marchesin"
#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
#define DRIVER_NAME "nouveau"
#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
#define DRIVER_DATE "20060213"
Merge the pciid work. Add getparams for AGP and FB physical adresses. Fix the MEM_ALLOC issue properly. Fix context switches for nv44. Change the DRM version to 0.0.1.
2006-12-03 02:02:54 -07:00
#define DRIVER_MAJOR 0
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
#define DRIVER_MINOR 0
nouveau: separate region_offset into map_handle and offset.
2007-07-11 18:15:16 -06:00
#define DRIVER_PATCHLEVEL 9
initial import of nouveau code from nouveau CVS
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#define NOUVEAU_FAMILY 0x0000FFFF
#define NOUVEAU_FLAGS 0xFFFF0000
#include "nouveau_drm.h"
#include "nouveau_reg.h"
nouveau: Add nv40-specific PGRAPH code, not hooked up yet.
2007-01-01 20:52:43 -07:00
struct mem_block {
struct mem_block *next;
struct mem_block *prev;
uint64_t start;
uint64_t size;
DRMFILE filp; /* 0: free, -1: heap, other: real files */
int flags;
drm_local_map_t *map;
nouveau: separate region_offset into map_handle and offset.
2007-07-11 18:15:16 -06:00
drm_handle_t map_handle;
nouveau: Add nv40-specific PGRAPH code, not hooked up yet.
2007-01-01 20:52:43 -07:00
};
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
enum nouveau_flags {
NV_NFORCE =0x10000000,
NV_NFORCE2 =0x20000000
};
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
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#define NVOBJ_ENGINE_SW 0
#define NVOBJ_ENGINE_GR 1
#define NVOBJ_ENGINE_INT 0xdeadbeef
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
#define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
#define NVOBJ_FLAG_FAKE (1 << 3)
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
struct nouveau_gpuobj {
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
struct nouveau_gpuobj *next;
struct nouveau_gpuobj *prev;
Use nouveau_mem.c to allocate RAMIN.
2006-11-29 16:31:42 -07:00
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
int im_channel;
struct mem_block *im_pramin;
struct mem_block *im_backing;
nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-04 08:12:33 -06:00
int im_bound;
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
uint32_t flags;
int refcount;
uint32_t engine;
uint32_t class;
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
};
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
struct nouveau_gpuobj_ref {
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
struct nouveau_gpuobj_ref *next;
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
struct nouveau_gpuobj *gpuobj;
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
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uint32_t instance;
int channel;
int handle;
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
};
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
struct nouveau_fifo
{
/* owner of this fifo */
DRMFILE filp;
/* mapping of the fifo itself */
drm_local_map_t *map;
/* mapping of the regs controling the fifo */
drm_local_map_t *regs;
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
/* DMA push buffer */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
struct nouveau_gpuobj_ref *pushbuf;
struct mem_block *pushbuf_mem;
uint32_t pushbuf_base;
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
/* Notifier memory */
nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7) For various reasons, this ioctl was a bad idea. At channel creation we now automatically create DMA objects covering available VRAM and GART memory, where the client used to do this themselves. However, there is still a need to be able to create DMA objects pointing at specific areas of memory (ie. notifiers). Each channel is now allocated a small amount of memory from which a client can suballocate things (such as notifiers), and have a DMA object created which covers the suballocated area. The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-24 03:03:35 -06:00
struct mem_block *notifier_block;
struct mem_block *notifier_heap;
drm_local_map_t *notifier_map;
Add basic pgraph context for nv10. It only fake a context switch : pgraph state are not save/restored.
2007-01-05 11:40:11 -07:00
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
/* PFIFO context */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
struct nouveau_gpuobj_ref *ramfc;
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
/* PGRAPH context */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
struct nouveau_gpuobj_ref *ramin_grctx;
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
uint32_t pgraph_ctx [340]; /* XXX dynamic alloc ? */
/* Objects */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
struct nouveau_gpuobj_ref *ramin; /* Private instmem */
struct mem_block *ramin_heap; /* Private PRAMIN heap */
struct nouveau_gpuobj_ref *ramht; /* Hash table */
struct nouveau_gpuobj_ref *ramht_refs; /* Objects referenced by RAMHT */
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
};
Allow cmdbuf location(AGP,VRAM) and size to be configured.
2006-09-02 14:36:06 -06:00
struct nouveau_config {
struct {
int location;
int size;
} cmdbuf;
};
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
struct nouveau_engine_func {
nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-04 08:12:33 -06:00
struct {
void *priv;
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
int (*init)(struct drm_device *dev);
void (*takedown)(struct drm_device *dev);
nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-04 08:12:33 -06:00
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-04 08:12:33 -06:00
uint32_t *size);
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-04 08:12:33 -06:00
} instmem;
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
struct {
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
int (*init)(struct drm_device *dev);
void (*takedown)(struct drm_device *dev);
nouveau: rename engtab functions
2007-06-24 02:54:36 -06:00
} mc;
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
struct {
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
int (*init)(struct drm_device *dev);
void (*takedown)(struct drm_device *dev);
nouveau: rename engtab functions
2007-06-24 02:54:36 -06:00
} timer;
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
struct {
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
int (*init)(struct drm_device *dev);
void (*takedown)(struct drm_device *dev);
nouveau: rename engtab functions
2007-06-24 02:54:36 -06:00
} fb;
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
struct {
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
int (*init)(struct drm_device *);
void (*takedown)(struct drm_device *);
nouveau: prototype PFIFO/PGRAPH engtab API
2007-06-24 02:54:51 -06:00
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
int (*create_context)(struct drm_device *, int channel);
void (*destroy_context)(struct drm_device *, int channel);
int (*load_context)(struct drm_device *, int channel);
int (*save_context)(struct drm_device *, int channel);
nouveau: rename engtab functions
2007-06-24 02:54:36 -06:00
} graph;
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
struct {
nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-04 08:12:33 -06:00
void *priv;
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
int (*init)(struct drm_device *);
void (*takedown)(struct drm_device *);
nouveau: prototype PFIFO/PGRAPH engtab API
2007-06-24 02:54:51 -06:00
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
int (*create_context)(struct drm_device *, int channel);
void (*destroy_context)(struct drm_device *, int channel);
int (*load_context)(struct drm_device *, int channel);
int (*save_context)(struct drm_device *, int channel);
nouveau: rename engtab functions
2007-06-24 02:54:36 -06:00
} fifo;
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
};
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
struct drm_nouveau_private {
nouveau: Avoid oops Turns out lastclose() gets called even if firstopen() has never been...
2007-07-08 23:37:37 -06:00
enum {
NOUVEAU_CARD_INIT_DOWN,
NOUVEAU_CARD_INIT_DONE,
NOUVEAU_CARD_INIT_FAILED
} init_state;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
/* the card type, takes NV_* as values */
int card_type;
nouveau: determine chipset type at startup, instead of every time we use it.
2007-01-28 05:48:33 -07:00
/* exact chipset, derived from NV_PMC_BOOT_0 */
int chipset;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
int flags;
drm_local_map_t *mmio;
drm_local_map_t *fb;
nouveau: map pci resource 2 on >=nv40
2007-01-07 05:56:45 -07:00
drm_local_map_t *ramin; /* NV40 onwards */
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
Hack around yet another "X restart borkage without nouveau.ko reload" problem. On X init, PFIFO and PGRAPH are reset to defaults. This causes the GPU to loose the configuration done by the drm. Perhaps a CARD_INIT ioctl a proper solution to having this problem again in the future..
2006-11-13 10:51:13 -07:00
int fifo_alloc_count;
nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-04 08:12:33 -06:00
struct nouveau_fifo *fifos[NV_MAX_FIFO_NUMBER];
Use nouveau_mem.c to allocate RAMIN.
2006-11-29 16:31:42 -07:00
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
struct nouveau_engine_func Engine;
nouveau: avoid allocating vram that's used as instance memory.
2007-01-07 06:37:39 -07:00
/* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
struct nouveau_gpuobj *ramht;
nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-04 08:12:33 -06:00
uint32_t ramin_rsvd_vram;
Restructure initialisation a bit. - Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-13 14:11:49 -07:00
uint32_t ramht_offset;
uint32_t ramht_size;
uint32_t ramht_bits;
Context switching work. Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet). Removed the PFIFO_REINIT ioctl. I hope it's that a good idea... Requires the upcoming commit to the DDX.
2006-10-10 16:28:15 -06:00
uint32_t ramfc_offset;
Restructure initialisation a bit. - Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-13 14:11:49 -07:00
uint32_t ramfc_size;
Context switching work. Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet). Removed the PFIFO_REINIT ioctl. I hope it's that a good idea... Requires the upcoming commit to the DDX.
2006-10-10 16:28:15 -06:00
uint32_t ramro_offset;
Restructure initialisation a bit. - Do important card init in firstopen - Give each channel it's own cmdbuf dma object - Move RAMHT config state to the same place as RAMRO/RAMFC - Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-13 14:11:49 -07:00
uint32_t ramro_size;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
Merge the pciid work. Add getparams for AGP and FB physical adresses. Fix the MEM_ALLOC issue properly. Fix context switches for nv44. Change the DRM version to 0.0.1.
2006-12-03 02:02:54 -07:00
/* base physical adresses */
uint64_t fb_phys;
nouveau: intrusive drm interface changes graphics objects: - No longer takes flags/dmaobj parameters, requires some major changes to the ddx to setup the object through the FIFO. This change is likely to cause breakages on some cards (tested on NV05,NV28,NV35, NV40 and NV4E). dma objects: - now takes a "class" parameter, not really used yet but we may need it at some point. - parameters are checked, so clients can't randomly create DMA objects pointing at whatever they feel like. misc: - Added FB_SIZE/AGP_SIZE getparams - Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR - Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't NOTIFICATION_PENDING.
2007-02-27 21:14:08 -07:00
uint64_t fb_available_size;
Merge the pciid work. Add getparams for AGP and FB physical adresses. Fix the MEM_ALLOC issue properly. Fix context switches for nv44. Change the DRM version to 0.0.1.
2006-12-03 02:02:54 -07:00
uint64_t agp_phys;
nouveau: intrusive drm interface changes graphics objects: - No longer takes flags/dmaobj parameters, requires some major changes to the ddx to setup the object through the FIFO. This change is likely to cause breakages on some cards (tested on NV05,NV28,NV35, NV40 and NV4E). dma objects: - now takes a "class" parameter, not really used yet but we may need it at some point. - parameters are checked, so clients can't randomly create DMA objects pointing at whatever they feel like. misc: - Added FB_SIZE/AGP_SIZE getparams - Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR - Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't NOTIFICATION_PENDING.
2007-02-27 21:14:08 -07:00
uint64_t agp_available_size;
Merge the pciid work. Add getparams for AGP and FB physical adresses. Fix the MEM_ALLOC issue properly. Fix context switches for nv44. Change the DRM version to 0.0.1.
2006-12-03 02:02:54 -07:00
nouveau: Add an mtrr over the whole FB
2007-01-05 12:49:34 -07:00
/* the mtrr covering the FB */
int fb_mtrr;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
struct mem_block *agp_heap;
struct mem_block *fb_heap;
struct mem_block *fb_nomap_heap;
Use nouveau_mem.c to allocate RAMIN.
2006-11-29 16:31:42 -07:00
struct mem_block *ramin_heap;
Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel.
2007-07-10 18:35:10 -06:00
struct mem_block *pci_heap;
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
nouveau: get nv30 context switching to work. * Pulled in some registers from nv10reg.h. Needed for context switching. * Filled in nv30 graphics context (based on nv40_graph.c). * Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-11 22:13:05 -07:00
/* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
uint32_t ctx_table_size;
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
struct nouveau_gpuobj_ref *ctx_table;
nouveau: get nv30 context switching to work. * Pulled in some registers from nv10reg.h. Needed for context switching. * Filled in nv30 graphics context (based on nv40_graph.c). * Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-11 22:13:05 -07:00
Allow cmdbuf location(AGP,VRAM) and size to be configured.
2006-09-02 14:36:06 -06:00
struct nouveau_config config;
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
struct nouveau_gpuobj *gpuobj_all;
};
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
/* nouveau_state.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern void nouveau_preclose(struct drm_device * dev, DRMFILE filp);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
extern int nouveau_load(struct drm_device *dev, unsigned long flags);
extern int nouveau_firstopen(struct drm_device *dev);
nouveau: Add an mtrr over the whole FB
2007-01-05 12:49:34 -07:00
extern void nouveau_lastclose(struct drm_device *dev);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
extern int nouveau_unload(struct drm_device *dev);
Add stub {get,set}param ioctls.
2006-08-30 00:55:02 -06:00
extern int nouveau_ioctl_getparam(DRM_IOCTL_ARGS);
extern int nouveau_ioctl_setparam(DRM_IOCTL_ARGS);
Context switching work. Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet). Removed the PFIFO_REINIT ioctl. I hope it's that a good idea... Requires the upcoming commit to the DDX.
2006-10-10 16:28:15 -06:00
extern void nouveau_wait_for_idle(struct drm_device *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
extern int nouveau_ioctl_card_init(DRM_IOCTL_ARGS);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
/* nouveau_mem.c */
nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7) For various reasons, this ioctl was a bad idea. At channel creation we now automatically create DMA objects covering available VRAM and GART memory, where the client used to do this themselves. However, there is still a need to be able to create DMA objects pointing at specific areas of memory (ie. notifiers). Each channel is now allocated a small amount of memory from which a client can suballocate things (such as notifiers), and have a DMA object created which covers the suballocated area. The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-24 03:03:35 -06:00
extern int nouveau_mem_init_heap(struct mem_block **,
uint64_t start, uint64_t size);
extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
uint64_t size, int align2,
DRMFILE);
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
extern void nouveau_mem_takedown(struct mem_block **heap);
nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7) For various reasons, this ioctl was a bad idea. At channel creation we now automatically create DMA objects covering available VRAM and GART memory, where the client used to do this themselves. However, there is still a need to be able to create DMA objects pointing at specific areas of memory (ie. notifiers). Each channel is now allocated a small amount of memory from which a client can suballocate things (such as notifiers), and have a DMA object created which covers the suballocated area. The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-24 03:03:35 -06:00
extern void nouveau_mem_free_block(struct mem_block *);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
extern uint64_t nouveau_mem_fb_amount(struct drm_device *dev);
extern void nouveau_mem_release(DRMFILE filp, struct mem_block *heap);
extern int nouveau_ioctl_mem_alloc(DRM_IOCTL_ARGS);
extern int nouveau_ioctl_mem_free(DRM_IOCTL_ARGS);
extern struct mem_block* nouveau_mem_alloc(struct drm_device *dev, int alignment, uint64_t size, int flags, DRMFILE filp);
extern void nouveau_mem_free(struct drm_device* dev, struct mem_block*);
extern int nouveau_mem_init(struct drm_device *dev);
extern void nouveau_mem_close(struct drm_device *dev);
nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7) For various reasons, this ioctl was a bad idea. At channel creation we now automatically create DMA objects covering available VRAM and GART memory, where the client used to do this themselves. However, there is still a need to be able to create DMA objects pointing at specific areas of memory (ie. notifiers). Each channel is now allocated a small amount of memory from which a client can suballocate things (such as notifiers), and have a DMA object created which covers the suballocated area. The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-24 03:03:35 -06:00
/* nouveau_notifier.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nouveau_notifier_init_channel(struct drm_device *, int channel, DRMFILE);
extern void nouveau_notifier_takedown_channel(struct drm_device *, int channel);
extern int nouveau_notifier_alloc(struct drm_device *, int channel,
nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7) For various reasons, this ioctl was a bad idea. At channel creation we now automatically create DMA objects covering available VRAM and GART memory, where the client used to do this themselves. However, there is still a need to be able to create DMA objects pointing at specific areas of memory (ie. notifiers). Each channel is now allocated a small amount of memory from which a client can suballocate things (such as notifiers), and have a DMA object created which covers the suballocated area. The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-24 03:03:35 -06:00
uint32_t handle, int cout, uint32_t *offset);
extern int nouveau_ioctl_notifier_alloc(DRM_IOCTL_ARGS);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
/* nouveau_fifo.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nouveau_fifo_init(struct drm_device *dev);
extern int nouveau_fifo_number(struct drm_device *dev);
extern int nouveau_fifo_ctx_size(struct drm_device *dev);
extern void nouveau_fifo_cleanup(struct drm_device *dev, DRMFILE filp);
extern int nouveau_fifo_owner(struct drm_device *dev, DRMFILE filp, int channel);
extern void nouveau_fifo_free(struct drm_device *dev, int channel);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
/* nouveau_object.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern void nouveau_gpuobj_takedown(struct drm_device *dev);
extern int nouveau_gpuobj_channel_init(struct drm_device *, int channel,
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
uint32_t vram_h, uint32_t tt_h);
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern void nouveau_gpuobj_channel_takedown(struct drm_device *, int channel);
extern int nouveau_gpuobj_new(struct drm_device *, int channel, int size, int align,
uint32_t flags, struct nouveau_gpuobj **);
extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
extern int nouveau_gpuobj_ref_add(struct drm_device *, int channel, uint32_t handle,
struct nouveau_gpuobj *,
struct nouveau_gpuobj_ref **);
extern int nouveau_gpuobj_ref_del(struct drm_device *, struct nouveau_gpuobj_ref **);
extern int nouveau_gpuobj_new_ref(struct drm_device *, int chan_obj, int chan_ref,
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
uint32_t handle, int size, int align,
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
uint32_t flags, struct nouveau_gpuobj_ref **);
extern int nouveau_gpuobj_new_fake(struct drm_device *, uint32_t offset,
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
uint32_t size, uint32_t flags,
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
struct nouveau_gpuobj**,
struct nouveau_gpuobj_ref**);
extern int nouveau_gpuobj_dma_new(struct drm_device *, int channel, int class,
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
uint64_t offset, uint64_t size,
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
int access, int target,
struct nouveau_gpuobj **);
extern int nouveau_gpuobj_gr_new(struct drm_device *, int channel, int class,
struct nouveau_gpuobj **);
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
extern int nouveau_ioctl_grobj_alloc(DRM_IOCTL_ARGS);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
/* nouveau_irq.c */
extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern void nouveau_irq_preinstall(struct drm_device*);
extern void nouveau_irq_postinstall(struct drm_device*);
extern void nouveau_irq_uninstall(struct drm_device*);
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
/* nv04_fb.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv04_fb_init(struct drm_device *dev);
extern void nv04_fb_takedown(struct drm_device *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
/* nv10_fb.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv10_fb_init(struct drm_device *dev);
extern void nv10_fb_takedown(struct drm_device *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
/* nv40_fb.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv40_fb_init(struct drm_device *dev);
extern void nv40_fb_takedown(struct drm_device *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
nouveau: NV04 PFIFO engtab functions
2007-06-24 02:57:09 -06:00
/* nv04_fifo.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv04_fifo_create_context(struct drm_device *dev, int channel);
extern void nv04_fifo_destroy_context(struct drm_device *dev, int channel);
extern int nv04_fifo_load_context(struct drm_device *dev, int channel);
extern int nv04_fifo_save_context(struct drm_device *dev, int channel);
nouveau: NV04 PFIFO engtab functions
2007-06-24 02:57:09 -06:00
nouveau: NV1X/2X/3X PFIFO engtab functions Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC entry size.
2007-06-24 02:58:14 -06:00
/* nv10_fifo.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv10_fifo_create_context(struct drm_device *dev, int channel);
extern void nv10_fifo_destroy_context(struct drm_device *dev, int channel);
extern int nv10_fifo_load_context(struct drm_device *dev, int channel);
extern int nv10_fifo_save_context(struct drm_device *dev, int channel);
nouveau: NV1X/2X/3X PFIFO engtab functions Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC entry size.
2007-06-24 02:58:14 -06:00
nouveau: NV4X PFIFO engtab functions
2007-06-24 02:56:01 -06:00
/* nv40_fifo.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv40_fifo_create_context(struct drm_device *, int channel);
extern void nv40_fifo_destroy_context(struct drm_device *, int channel);
extern int nv40_fifo_load_context(struct drm_device *, int channel);
extern int nv40_fifo_save_context(struct drm_device *, int channel);
nouveau: NV4X PFIFO engtab functions
2007-06-24 02:56:01 -06:00
nouveau/nv50: skeletal backend
2007-06-24 04:49:19 -06:00
/* nv50_fifo.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv50_fifo_init(struct drm_device *);
extern void nv50_fifo_takedown(struct drm_device *);
extern int nv50_fifo_create_context(struct drm_device *, int channel);
extern void nv50_fifo_destroy_context(struct drm_device *, int channel);
extern int nv50_fifo_load_context(struct drm_device *, int channel);
extern int nv50_fifo_save_context(struct drm_device *, int channel);
nouveau/nv50: skeletal backend
2007-06-24 04:49:19 -06:00
nouveau: and of course, I was missing the last nv04 piece.
2007-02-02 22:13:27 -07:00
/* nv04_graph.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern void nouveau_nv04_context_switch(struct drm_device *dev);
extern int nv04_graph_init(struct drm_device *dev);
extern void nv04_graph_takedown(struct drm_device *dev);
extern int nv04_graph_create_context(struct drm_device *dev, int channel);
extern void nv04_graph_destroy_context(struct drm_device *dev, int channel);
extern int nv04_graph_load_context(struct drm_device *dev, int channel);
extern int nv04_graph_save_context(struct drm_device *dev, int channel);
nouveau: and of course, I was missing the last nv04 piece.
2007-02-02 22:13:27 -07:00
nouveau: first step to make graph ctx works It is still not working, but now we could use some 3D commands without needed to run nvidia blob before.
2007-01-13 13:43:47 -07:00
/* nv10_graph.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern void nouveau_nv10_context_switch(struct drm_device *dev);
extern int nv10_graph_init(struct drm_device *dev);
extern void nv10_graph_takedown(struct drm_device *dev);
extern int nv10_graph_create_context(struct drm_device *dev, int channel);
extern void nv10_graph_destroy_context(struct drm_device *dev, int channel);
extern int nv10_graph_load_context(struct drm_device *dev, int channel);
extern int nv10_graph_save_context(struct drm_device *dev, int channel);
nouveau: first step to make graph ctx works It is still not working, but now we could use some 3D commands without needed to run nvidia blob before.
2007-01-13 13:43:47 -07:00
nouveau: nv20 graph ctx switch. Untested...
2007-01-13 15:19:41 -07:00
/* nv20_graph.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern void nouveau_nv20_context_switch(struct drm_device *dev);
extern int nv20_graph_init(struct drm_device *dev);
extern void nv20_graph_takedown(struct drm_device *dev);
extern int nv20_graph_create_context(struct drm_device *dev, int channel);
extern void nv20_graph_destroy_context(struct drm_device *dev, int channel);
extern int nv20_graph_load_context(struct drm_device *dev, int channel);
extern int nv20_graph_save_context(struct drm_device *dev, int channel);
nouveau: nv20 graph ctx switch. Untested...
2007-01-13 15:19:41 -07:00
nouveau: get nv30 context switching to work. * Pulled in some registers from nv10reg.h. Needed for context switching. * Filled in nv30 graphics context (based on nv40_graph.c). * Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-11 22:13:05 -07:00
/* nv30_graph.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv30_graph_init(struct drm_device *dev);
extern void nv30_graph_takedown(struct drm_device *dev);
extern int nv30_graph_create_context(struct drm_device *, int channel);
extern void nv30_graph_destroy_context(struct drm_device *, int channel);
extern int nv30_graph_load_context(struct drm_device *, int channel);
extern int nv30_graph_save_context(struct drm_device *, int channel);
nouveau: get nv30 context switching to work. * Pulled in some registers from nv10reg.h. Needed for context switching. * Filled in nv30 graphics context (based on nv40_graph.c). * Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-11 22:13:05 -07:00
nouveau: Add nv40-specific PGRAPH code, not hooked up yet.
2007-01-01 20:52:43 -07:00
/* nv40_graph.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv40_graph_init(struct drm_device *);
extern void nv40_graph_takedown(struct drm_device *);
extern int nv40_graph_create_context(struct drm_device *, int channel);
extern void nv40_graph_destroy_context(struct drm_device *, int channel);
extern int nv40_graph_load_context(struct drm_device *, int channel);
extern int nv40_graph_save_context(struct drm_device *, int channel);
nouveau: Add nv40-specific PGRAPH code, not hooked up yet.
2007-01-01 20:52:43 -07:00
nouveau/nv50: skeletal backend
2007-06-24 04:49:19 -06:00
/* nv50_graph.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv50_graph_init(struct drm_device *);
extern void nv50_graph_takedown(struct drm_device *);
extern int nv50_graph_create_context(struct drm_device *, int channel);
extern void nv50_graph_destroy_context(struct drm_device *, int channel);
extern int nv50_graph_load_context(struct drm_device *, int channel);
extern int nv50_graph_save_context(struct drm_device *, int channel);
nouveau/nv50: skeletal backend
2007-06-24 04:49:19 -06:00
nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-04 08:12:33 -06:00
/* nv04_instmem.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv04_instmem_init(struct drm_device *dev);
extern void nv04_instmem_takedown(struct drm_device *dev);
extern int nv04_instmem_populate(struct drm_device*, struct nouveau_gpuobj*,
nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-04 08:12:33 -06:00
uint32_t *size);
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern void nv04_instmem_clear(struct drm_device*, struct nouveau_gpuobj*);
extern int nv04_instmem_bind(struct drm_device*, struct nouveau_gpuobj*);
extern int nv04_instmem_unbind(struct drm_device*, struct nouveau_gpuobj*);
nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-04 08:12:33 -06:00
/* nv50_instmem.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv50_instmem_init(struct drm_device *dev);
extern void nv50_instmem_takedown(struct drm_device *dev);
extern int nv50_instmem_populate(struct drm_device*, struct nouveau_gpuobj*,
nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-04 08:12:33 -06:00
uint32_t *size);
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern void nv50_instmem_clear(struct drm_device*, struct nouveau_gpuobj*);
extern int nv50_instmem_bind(struct drm_device*, struct nouveau_gpuobj*);
extern int nv50_instmem_unbind(struct drm_device*, struct nouveau_gpuobj*);
nouveau/nv50: Initial channel/object support Should be OK on G84 for a single channel, multiple channels *almost* work. Untested on G80.
2007-07-04 08:12:33 -06:00
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
/* nv04_mc.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv04_mc_init(struct drm_device *dev);
extern void nv04_mc_takedown(struct drm_device *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
/* nv40_mc.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv40_mc_init(struct drm_device *dev);
extern void nv40_mc_takedown(struct drm_device *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
nouveau/nv50: skeletal backend
2007-06-24 04:49:19 -06:00
/* nv50_mc.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv50_mc_init(struct drm_device *dev);
extern void nv50_mc_takedown(struct drm_device *dev);
nouveau/nv50: skeletal backend
2007-06-24 04:49:19 -06:00
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
/* nv04_timer.c */
nouveau: nuke internal typedefs, and drm_device_t use.
2007-07-12 23:09:31 -06:00
extern int nv04_timer_init(struct drm_device *dev);
extern void nv04_timer_takedown(struct drm_device *dev);
nouveau: move card initialisation into the drm The PGRAPH init for the various cards will need cleaning up at some point, a lot of the values written there are per-context state left over from the all the hardcoding done in the ddx. It's possible some cards get broken by this commit, let me know. Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 03:43:48 -06:00
nouveau: add compat ioc32 support
2006-11-05 02:38:44 -07:00
extern long nouveau_compat_ioctl(struct file *filp, unsigned int cmd,
unsigned long arg);
add powerpc mmio swapper to NV_READ/WRITE macros
2006-11-05 01:46:53 -07:00
#if defined(__powerpc__)
#define NV_READ(reg) in_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) )
#define NV_WRITE(reg,val) out_be32((void __iomem *)(dev_priv->mmio)->handle + (reg) , (val) )
#else
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
#define NV_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
#define NV_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
add powerpc mmio swapper to NV_READ/WRITE macros
2006-11-05 01:46:53 -07:00
#endif
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
nouveau: simplify PRAMIN access
2007-06-24 23:16:19 -06:00
/* PRAMIN access */
#if defined(__powerpc__)
#define NV_RI32(o) in_be32((void __iomem *)(dev_priv->ramin)->handle+(o))
#define NV_WI32(o,v) out_be32((void __iomem*)(dev_priv->ramin)->handle+(o), (v))
#else
#define NV_RI32(o) DRM_READ32(dev_priv->ramin, (o))
#define NV_WI32(o,v) DRM_WRITE32(dev_priv->ramin, (o), (v))
#endif
nouveau: rewrite gpu object code Allows multiple references to a single object, needed to support PCI(E)GART scatter-gather DMA objects which would quickly fill PRAMIN if each channel had its own. Handle per-channel private instmem areas. This is needed to support NV50, but might be something we want to do on earlier chipsets at some point? Everything that touches PRAMIN is a GPU object.
2007-07-02 03:31:18 -06:00
#define INSTANCE_RD(o,i) NV_RI32((o)->im_pramin->start + ((i)<<2))
#define INSTANCE_WR(o,i,v) NV_WI32((o)->im_pramin->start + ((i)<<2), (v))
Wrap access to objects in RAMIN. This will make it easier to support extra RAMIN in vram at a later point.
2006-11-29 14:35:42 -07:00
initial import of nouveau code from nouveau CVS
2006-08-26 16:55:02 -06:00
#endif /* __NOUVEAU_DRV_H__ */