Commit Graph

66 Commits (205403aea8213ffc0e36f4103d78d62bf1584a69)

Author SHA1 Message Date
Pekka Paalanen 205403aea8 nouveau: nv30 graph function renames, removed nv20_graph.c
All nv30 functions in nv30_graph.c that can be used on nv20 are renamed
as accordingly. nv20 specific parts from nv20_graph.c are moved into
nv30_graph.c.
2007-09-30 22:16:01 +03:00
Matthieu Castet fb3ed99fb1 nouveau : pgraph_ctx dynamic alloc for nv04, nv10 2007-09-30 14:50:22 +02:00
Ben Skeggs c3faa589b0 nouveau: Allow GART notifiers when using sgdma code. 2007-08-15 13:36:54 +10:00
Ben Skeggs 02c4e0e757 nouveau/nv40: Fix channel scheduling.
Ensure NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLE gets set, otherwise channels
will appear to "freeze" in some circumstances.
2007-08-15 01:04:41 +10:00
Ben Skeggs a46104674f nouveau/nv50: demagic instmem setup. 2007-08-10 14:22:50 +10:00
Ben Skeggs 39907f613b nouveau: Allow creation of gpuobjs before any other init has taken place. 2007-08-10 13:53:10 +10:00
Ben Skeggs 05633ca370 nouveau: Always allocate drm's push buffer in VRAM
Fixes #11868
2007-08-08 16:37:55 +10:00
Ben Skeggs cf04641bc6 nouveau: Give DRM its own gpu channel
If your card doesn't have working context switching, it is now broken.
2007-08-06 22:05:31 +10:00
Ben Skeggs 97770db720 nouveau: Various internal and external API changes
1. DRM_NOUVEAU_GPUOBJ_FREE
	Used to free GPU objects.  The obvious usage case is for Gr objects,
	but notifiers can also be destroyed in the same way.

	GPU objects gain a destructor method and private data fields with
	this change, so other specialised cases (like notifiers) can be
	implemented on top of gpuobjs.

2. DRM_NOUVEAU_CHANNEL_FREE

3. DRM_NOUVEAU_CARD_INIT
	Ideally we'd do init during module load, but this isn't currently
	possible.  Doing init during firstopen() is bad as X has a love of
	opening/closing the DRM many times during startup.  Once the
	modesetting-101 branch is merged this can go away.

	IRQs are enabled in nouveau_card_init() now, rather than having the
	X server call drmCtlInstHandler().  We'll need this for when we give
	the kernel module its own channel.

4. DRM_NOUVEAU_GETPARAM
	Add CHIPSET_ID value, which will return the chipset id derived
	from NV_PMC_BOOT_0.

4. Use list_* in a few places, rather than home-brewed stuff.
2007-08-06 21:45:18 +10:00
Ben Skeggs beaa0c9a28 nouveau: Pass channel struct around instead of channel id. 2007-08-06 03:40:43 +10:00
Eric Anholt 5b38e13416 Replace DRM_IOCTL_ARGS with (dev, data, file_priv) and remove DRM_DEVICE.
The data is now in kernel space, copied in/out as appropriate according to the
This results in DRM_COPY_{TO,FROM}_USER going away, and error paths to deal
with those failures.  This also means that XFree86 4.2.0 support for i810 DRM
is lost.
2007-07-20 18:16:42 -07:00
Eric Anholt c1119b1b09 Replace filp in ioctl arguments with drm_file *file_priv.
As a fallout, replace filp storage with file_priv storage for "unique
identifier of a client" all over the DRM.  There is a 1:1 mapping, so this
should be a noop.  This could be a minor performance improvement, as everything
on Linux dereferenced filp to get file_priv anyway, while only the mmap ioctls
went the other direction.
2007-07-20 13:39:45 -07:00
Pekka Paalanen 696bee093f nouveau: Add read() method to Engine.timer.
This is not called from anywhere, yet.
2007-07-18 14:12:26 +03:00
Ben Skeggs ec67c2def9 nouveau: G8x PCIEGART
Actually a NV04-NV50 ttm backend for both PCI and PCIEGART, but PCIGART
support for G8X using the current mm has been hacked on top of it.
2007-07-17 13:51:14 +10:00
Ben Skeggs 0029713451 nouveau: nuke internal typedefs, and drm_device_t use. 2007-07-13 15:09:31 +10:00
Ben Skeggs 750371cb6e nouveau: separate region_offset into map_handle and offset. 2007-07-12 10:46:57 +10:00
Arthur Huillet 694e1c5c3f Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel. 2007-07-11 02:35:10 +02:00
Ben Skeggs 3c58195ccd nouveau: Avoid oops
Turns out lastclose() gets called even if firstopen() has never been...
2007-07-09 16:16:44 +10:00
Ben Skeggs c806bba466 nouveau/nv50: Initial channel/object support
Should be OK on G84 for a single channel, multiple channels *almost* work.

Untested on G80.
2007-07-09 16:16:44 +10:00
Ben Skeggs 163f852612 nouveau: rewrite gpu object code
Allows multiple references to a single object, needed to support PCI(E)GART
scatter-gather DMA objects which would quickly fill PRAMIN if each channel
had its own.

Handle per-channel private instmem areas.  This is needed to support NV50,
but might be something we want to do on earlier chipsets at some point?

Everything that touches PRAMIN is a GPU object.
2007-07-09 16:16:44 +10:00
Ben Skeggs 68ecf61647 nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bit 2007-06-28 03:26:44 +10:00
Ben Skeggs 18a6d1c9c3 nouveau: simplify PRAMIN access 2007-06-28 03:26:44 +10:00
Ben Skeggs ce0d528d3c nouveau/nv50: skeletal backend 2007-06-28 03:26:43 +10:00
Ben Skeggs 695599f18d nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)
For various reasons, this ioctl was a bad idea.

At channel creation we now automatically create DMA objects covering
available VRAM and GART memory, where the client used to do this themselves.

However, there is still a need to be able to create DMA objects pointing at
specific areas of memory (ie. notifiers).  Each channel is now allocated a
small amount of memory from which a client can suballocate things (such as
notifiers), and have a DMA object created which covers the suballocated area.
The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-28 03:26:43 +10:00
Ben Skeggs 5f05cd7086 nouveau: NV04/NV10/NV20 PGRAPH engtab functions
NV04/NV10 load_context()/save_context() are stubs.  I don't know enough about
how they work to implement them sanely.  The "old" context_switch() code
remains hooked up, so it shouldn't break anything.

NV20 will probably break if load_context() works.  No inital context values
are filled in, so when the first channel is created PGRAPH will probably end
up having its state zeroed.  Some setup from nv20_graph_init() will probably
need to be moved to the per-channel context setup.
2007-06-24 19:00:26 +10:00
Ben Skeggs 5d55b0655c nouveau: NV3X PGRAPH engtab functions 2007-06-24 18:58:38 +10:00
Ben Skeggs 341bc78207 nouveau: NV1X/2X/3X PFIFO engtab functions
Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC
entry size.
2007-06-24 18:58:14 +10:00
Ben Skeggs 05d86d950a nouveau: NV04 PFIFO engtab functions 2007-06-24 18:57:09 +10:00
Ben Skeggs acb710d1a5 nouveau: NV4X PGRAPH engtab functions 2007-06-24 18:56:40 +10:00
Ben Skeggs f2e64d5276 nouveau: NV4X PFIFO engtab functions 2007-06-24 18:56:01 +10:00
Ben Skeggs 9dbf322d26 nouveau: (mostly) hook up put_base again 2007-06-24 18:55:06 +10:00
Ben Skeggs 24b71c318a nouveau: prototype PFIFO/PGRAPH engtab API 2007-06-24 18:54:51 +10:00
Ben Skeggs 5c7c07fd49 nouveau: rename engtab functions 2007-06-24 18:54:36 +10:00
Ben Skeggs 674cefd4fe nouveau: move card initialisation into the drm
The PGRAPH init for the various cards will need cleaning up at some point,
a lot of the values written there are per-context state left over from the
all the hardcoding done in the ddx.

It's possible some cards get broken by this commit, let me know.
Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 20:59:37 +10:00
Ben Skeggs 2bb9de96d5 nouveau: remove unused cruft 2007-03-23 13:45:29 +11:00
Ben Skeggs e22225416a nouveau: support multiple channels per client (breaks drm interface) 2007-03-21 17:57:47 +11:00
Ben Skeggs 90f8c691a5 nouveau: make sure cmdbuf object gets destroyed 2007-03-13 14:55:54 +11:00
Ben Skeggs 1775202cf9 nouveau: associate all created objects with a channel + cleanups 2007-03-13 14:55:54 +11:00
Ben Skeggs 72caa48c82 nouveau: intrusive drm interface changes
graphics objects:
	- No longer takes flags/dmaobj parameters, requires some major changes
	  to the ddx to setup the object through the FIFO.  This change is
	  likely to cause breakages on some cards (tested on NV05,NV28,NV35,
	  NV40 and NV4E).
dma objects:
	- now takes a "class" parameter, not really used yet but we may need
	  it at some point.
	- parameters are checked, so clients can't randomly create DMA objects
	  pointing at whatever they feel like.
misc:
	- Added FB_SIZE/AGP_SIZE getparams
	- Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR
	- Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't
	  NOTIFICATION_PENDING.
2007-02-28 15:41:53 +11:00
Stephane Marchesin 8c663b4e56 nouveau: and of course, I was missing the last nv04 piece. 2007-02-03 06:13:27 +01:00
Stephane Marchesin d69902db3b nouveau: fix nv04 graph routines for new register names. 2007-02-03 05:25:36 +01:00
Ben Skeggs ee4ac5c897 nouveau: determine chipset type at startup, instead of every time we use it. 2007-01-28 23:48:33 +11:00
Ben Skeggs 19ba074938 nouveau: fix getparam from 32-bit client on 64-bit kernel 2007-01-19 15:41:51 +11:00
Matthieu Castet f04347f371 nouveau: nv20 graph ctx switch.
Untested...
2007-01-13 23:19:41 +01:00
Matthieu Castet cd5f543b2f nouveau: first step to make graph ctx works
It is still not working, but now we could use some 3D commands
without needed to run nvidia blob before.
2007-01-13 21:44:50 +01:00
Jeremy Kolb 4297a83b48 nouveau: get nv30 context switching to work.
* Pulled in some registers from nv10reg.h.  Needed for context switching.
* Filled in nv30 graphics context (based on nv40_graph.c).
* Figure out nv30 context table, set up on context creation.  Allows the cards automatic switching to work.
2007-01-12 00:14:54 -05:00
Ben Skeggs faa4612299 nouveau: avoid allocating vram that's used as instance memory. 2007-01-08 00:44:02 +11:00
Ben Skeggs cd3711455e nouveau: map pci resource 2 on >=nv40 2007-01-08 00:44:02 +11:00
Stephane Marchesin d99c7c27e2 Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm 2007-01-05 20:50:46 +01:00
Stephane Marchesin 025f281bbf nouveau: Add an mtrr over the whole FB 2007-01-05 20:49:34 +01:00