fee64980c4
radeon_ms: another fb fix reset mode if fb changed
2008-04-07 20:49:36 +02:00
27c3785d3f
Add DragonFly BSD support for device creation
...
DragonFly behaves just like FreeBSD in this regard.
2008-04-07 15:27:43 +03:00
dfa9f03992
nouveau: enable accelerated move to sysmem
2008-04-07 13:29:11 +10:00
c12b60b509
nouveau: enable m2mf for tt<->vram moves, fix fence_poll
2008-04-07 13:05:51 +10:00
060e725a0e
radeon_ms: fix framebuffer code
2008-04-06 19:23:20 +02:00
91bfd69745
radeon_ms: check for NULL fb
2008-04-06 19:01:31 +02:00
e89710bef7
Place highmem pages last in the ttm page array.
2008-04-06 11:21:22 +02:00
c3888b97f6
Use clflush() when available for cache flushing.
2008-04-06 10:32:02 +02:00
51a0fdcf3f
[I915] Fix VRAM eviction.
2008-04-06 10:30:27 +02:00
87ae5b22e3
Fix emergency allocation accounting.
2008-04-06 10:30:27 +02:00
1692d30cea
nv50: primitive i2c interrupt handler
2008-04-05 21:02:00 +02:00
dfc8d2b2fe
radeon_ms: add crtc set base callback & fix palette
2008-04-03 03:15:47 +02:00
4dfb959238
radeon_ms: fixes fb handling
2008-04-03 03:14:52 +02:00
3fc444a5e8
nv50: primitive display interrupt handler.
2008-04-03 01:13:31 +02:00
9600423458
radeon_ms: small fix & cleanup to command checking
2008-03-31 21:50:02 +02:00
562f95ea96
nouveau: fix return from function..
...
dude kernel moduless use kernel errors :)
this fixes an oops on init when this codepath hits.
2008-03-31 11:34:48 +10:00
09e637848a
radeon_ms: initial pass at command buffer validation
2008-03-31 00:55:05 +02:00
22d931f966
Initialize the fence::error member.
2008-03-30 21:30:43 +02:00
1f4ba62567
[i915] Report buffer state _after_ fence submission to user-space.
...
This fixes a problem where the wrong bo->fence_type was reported, and
also saves some memory space.
[bo core] export the drm_bo_fill_rep_arg function.
2008-03-30 15:14:45 +02:00
b8567bafff
Don't call fence::poll during irq if there are no waiters.
2008-03-30 15:11:47 +02:00
cf3c0123a0
nouveau: forgot to add a break
2008-03-30 14:50:41 +02:00
68b83a8813
nouveau: Add ctx values for nv86.
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- Note that this may not work for all nv86.
2008-03-30 14:48:55 +02:00
2d9eccfd05
radeon_ms: add hang debuging helper functions
2008-03-30 12:50:26 +02:00
753a4bdf1b
drm/r300: fix wait interface mixup
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This interface was defined completely wrong, however userspace has only
ever used 4 values from it (0x1, 0x2, 0x3 and 0x6), so fix the interface to do what userspace actually expected but define new defines for new users to use
it properly.
2008-03-30 07:33:39 +10:00
1674d28179
r300: Correctly translate the value for the R300_CMD_WAIT command.
...
Previously, the R300_CMD_WAIT command would write the passed directly to the
hardware. However this is incorrect because the R300_WAIT_* values used are
internal interface values that do not map directly to the hardware.
The new function I have added translates the R300_WAIT_* values into appropriate
values for the hardware before writing the register.
Thanks to John Bridgman for pointing this out. :-)
2008-03-29 17:31:39 +00:00
0da289bafd
radeon_ms: this is a modesetting driver, bring things up to date
2008-03-27 20:08:37 +01:00
acb6c9ef97
drm: remove authentication on master exit.
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using contexts for this is bad for multiple masters
2008-03-27 15:55:49 +10:00
a81d07f64d
nouveau: nv20 bios does not initialise PTIMER
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The wait functions depend on PTIMER, so write the old (incorrect, but working) values for uninitialised hw
2008-03-25 18:32:26 +00:00
b0817a42e7
i915: fix oops on agp=off
...
Kernel bug 10289.
2008-03-24 18:52:26 +10:00
4323ee3e5b
Merge branch 'r500-fp'
2008-03-24 18:47:50 +10:00
a244d29050
nouveau: silence warning
2008-03-24 03:26:37 +11:00
24ba0c9c3b
nv40: voodoo - not quite.
2008-03-24 03:26:34 +11:00
6f4b3de284
nv40: allocate massive amount of PRAMIN for grctx on all chipsets.
...
More or less a workaround for issues on some chipsets where a context
switch results in critical data in PRAMIN being overwritten by the GPU.
The correct fix is known, but may take some time before it's a feasible
option.
2008-03-24 03:26:30 +11:00
36e11dd380
r500: fragment program upload is also used to upload constants.
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Limit frag address to 8 bits
2008-03-21 16:59:52 +10:00
71b66b0043
Merge branch 'modesetting-101' of ssh://git.freedesktop.org/git/mesa/drm into modesetting-101
2008-03-20 17:44:32 +01:00
6ef119abf5
radeon_ms: fix fence
2008-03-20 17:43:43 +01:00
316979356f
drm: fixup r500fp submission
2008-03-20 14:20:53 +10:00
1021799b6c
nouveau: do not set on-board timer's numerator/denominator to bad values
2008-03-20 02:57:58 +00:00
9e4f908287
RADEON: switch over to new production microcode
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This needs to be tested thoroughly before pushing to the
kernel.
2008-03-19 15:37:56 -04:00
d8af16d2a7
RADEON: production microcode for all radeons, r1xx-r6xx
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This updated microcode is not in use yet.
2008-03-19 14:57:42 -04:00
a3c808d8fe
move some more r300 regs into not allowed on r500
2008-03-19 16:10:37 +10:00
d18c2c6842
drm: add new rs690 pci id
2008-03-18 09:07:45 +10:00
602800a280
Evict cached_mapped relocatee before applying reloc.
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Fix that got left out after the intel-post-reloc merge.
2008-03-17 11:38:46 +01:00
607964ed9e
drm: add master set/drop protocol
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this may not survive long - just need something for testing
2008-03-17 16:38:20 +10:00
2d0411cb75
i915: safety check the sarea map still exists
2008-03-17 16:38:18 +10:00
e6be93b2a6
drm: pick correct master for cleaning up
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When a master is exiting, make sure we clean it up and not the currently
in charge master.
2008-03-17 16:38:17 +10:00
d1513528d7
drm: select the correct master to attempt to remove the lock from.
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When destroying DRI sarea, make sure you use the master associated with the
sarea and not the one currently in charge
2008-03-17 16:38:15 +10:00
3add949403
initial r500 RS and FP register and upload code
2008-03-17 11:08:03 +10:00
1f96e9a982
drm/pcigart: fix the pci gart to use the drm_pci wrapper.
...
This is the correct fix for the RS690 and hopefully the dma coherent work.
For now we limit everybody to a 32-bit DMA mask but it is possible for
RS690 to use a 40-bit DMA mask for the GART table itself,
and the PCIE cards can use 40-bits for the table entries.
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-03-17 07:05:46 +10:00
1a2d8c4bfa
Avoid unnecessary waits for command regulator pause.
2008-03-16 20:07:14 +01:00
Jerome Glisse
Hasso Tepper
Ben Skeggs
Thomas Hellstrom
Maarten Maathuis
Dave Airlie
Thomas Hellström
Oliver McFadden
Stuart Bennett
Alex Deucher
Alex Deucher
Dave Airlie
Dave Airlie