1674d28179
r300: Correctly translate the value for the R300_CMD_WAIT command.
...
Previously, the R300_CMD_WAIT command would write the passed directly to the
hardware. However this is incorrect because the R300_WAIT_* values used are
internal interface values that do not map directly to the hardware.
The new function I have added translates the R300_WAIT_* values into appropriate
values for the hardware before writing the register.
Thanks to John Bridgman for pointing this out. :-)
2008-03-29 17:31:39 +00:00
a81d07f64d
nouveau: nv20 bios does not initialise PTIMER
...
The wait functions depend on PTIMER, so write the old (incorrect, but working) values for uninitialised hw
2008-03-25 18:32:26 +00:00
b0817a42e7
i915: fix oops on agp=off
...
Kernel bug 10289.
2008-03-24 18:52:26 +10:00
4323ee3e5b
Merge branch 'r500-fp'
2008-03-24 18:47:50 +10:00
24ba0c9c3b
nv40: voodoo - not quite.
2008-03-24 03:26:34 +11:00
6f4b3de284
nv40: allocate massive amount of PRAMIN for grctx on all chipsets.
...
More or less a workaround for issues on some chipsets where a context
switch results in critical data in PRAMIN being overwritten by the GPU.
The correct fix is known, but may take some time before it's a feasible
option.
2008-03-24 03:26:30 +11:00
36e11dd380
r500: fragment program upload is also used to upload constants.
...
Limit frag address to 8 bits
2008-03-21 16:59:52 +10:00
316979356f
drm: fixup r500fp submission
2008-03-20 14:20:53 +10:00
1021799b6c
nouveau: do not set on-board timer's numerator/denominator to bad values
2008-03-20 02:57:58 +00:00
9e4f908287
RADEON: switch over to new production microcode
...
This needs to be tested thoroughly before pushing to the
kernel.
2008-03-19 15:37:56 -04:00
d8af16d2a7
RADEON: production microcode for all radeons, r1xx-r6xx
...
This updated microcode is not in use yet.
2008-03-19 14:57:42 -04:00
a3c808d8fe
move some more r300 regs into not allowed on r500
2008-03-19 16:10:37 +10:00
d18c2c6842
drm: add new rs690 pci id
2008-03-18 09:07:45 +10:00
3add949403
initial r500 RS and FP register and upload code
2008-03-17 11:08:03 +10:00
1f96e9a982
drm/pcigart: fix the pci gart to use the drm_pci wrapper.
...
This is the correct fix for the RS690 and hopefully the dma coherent work.
For now we limit everybody to a 32-bit DMA mask but it is possible for
RS690 to use a 40-bit DMA mask for the GART table itself,
and the PCIE cards can use 40-bits for the table entries.
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-03-17 07:05:46 +10:00
1a2d8c4bfa
Avoid unnecessary waits for command regulator pause.
2008-03-16 20:07:14 +01:00
3a3a9485aa
[via] Remove some leftover vars.
2008-03-16 11:45:58 +01:00
7d3d15e67d
[via] The millionth fixup for the millionth-1 attempt to stabilize the AGP
...
DMA command submission. It's worth remembering that all new bright ideas on how
to make this command reader work properly and according to docs
will probably fail :( Bring in some old code.
2008-03-16 11:45:57 +01:00
563fe9dcd4
[via] Fix driver after vblank-rework merge.
2008-03-16 11:45:57 +01:00
5b1d9263d3
drm/rs690: set AGP_BASE_2 to 0
2008-03-16 14:00:16 +10:00
dd9eb923ed
drm: set rs690 gart base completly.
...
The docs state bits 4-11 represent bits 32-39 of a 40-bit address
2008-03-16 12:58:07 +10:00
9be916f353
Fix chip family for RV550
2008-03-12 11:16:12 -04:00
1766e1c07b
nv50: force channel vram access through vm
...
If we ever want to be able to use the 3D engine we have no choice. It
appears that the tiling setup (required for 3D on G8x) is in the page tables.
The immediate benefit of this change however is that it's now not possible
for a client to use the GPU to render over the top of important engine setup
tables, which also live in VRAM.
G8x VRAM size is limited to 512MiB at the moment, as we use a 1-1 mapping
of real vram pages to their offset within the start of a channel's VRAM
DMA object and only populate a single PDE for VRAM use.
2008-03-13 00:23:52 +11:00
88bd1e4a35
Merge branch 'intel-post-reloc'
...
Conflicts:
linux-core/drm_compat.c
linux-core/drm_compat.h
linux-core/drm_ttm.c
shared-core/i915_dma.c
Bump driver minor to 13 due to introduction of new
relocation type.
2008-03-12 11:34:29 +01:00
8a18d123f5
Avoid large kmallocs.
2008-03-12 09:49:27 +01:00
f13936f7fc
nouveau: move AGP reset to mem_init_agp
...
Also, power cycle PGRAPH when resetting AGP -- it seems to fix problems encountered by p0g on nv25
2008-03-11 16:45:35 +00:00
2848f04861
Switch from PIPE_VBLANK to PIPE_EVENT interrupts.
...
My 965GM gets interrupts stuck when using the old PIPE_VBLANK interrupt.
Switch to the PIPE_EVENT interrupt mechanism, and set the PIPE*STAT
registers to use START_VBLANK on 965 and VBLANK on previous chips.
2008-03-08 00:04:30 -08:00
ce3733572e
drm/radeon: check sarea_priv exists
2008-03-08 08:30:30 +10:00
1ccccbd4ce
nouveau: redo channel idle detection
...
Will hopefully work a bit better than previous code, which depended on
knowing the channel's most recent PUT value. Some chips always return
0 on reading these regs, and currently userspace is the only other entity
which knows the value.
2008-03-07 15:18:34 +11:00
cd924de029
nouveau: don't touch NV_USER regs on channel destroy.
...
Not only was this entirely pointless, it actually causes my NV30GL to
die randomly when channels are destroyed.
2008-03-07 15:18:34 +11:00
d5c0101252
ttm: make sure userspace can't destroy kernel create memory managers
...
this adds something to say the kernel initialised the memory region not
the userspace. and blocks userspace from deallocating kernel areas
2008-03-06 05:37:54 +10:00
180c9188f4
drm/ttm: add ioctl to get back memory managed area sized
...
taken from modesetting branch but could be useful outside it.
2008-03-06 05:31:50 +10:00
12574590cd
drm: reorganise minor number handling using code from modesetting branch
...
Rip out the whole head thing and replace it with an idr and drm_minor
structure.
2008-03-06 05:21:50 +10:00
638353103d
i915: Evict if relocatee buffer is CACHED_MAPPED before
...
writting relocations, otherwise the GPU probably sees some
inconsistent data. Fix fd.o bug#14656
2008-03-05 15:09:17 +08:00
a6a2f2c8c4
Clarify when WAIT_LAZY is relevant to users.
2008-03-04 13:45:41 -08:00
3332a0add6
Remove unused DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS.
2008-03-04 13:41:30 -08:00
63fd6f284d
[i915] 2D driver may reset Frame count value, this may lead driver
...
to leap it's vblank count a huge value.
This will stall some applications that switch video mode if vblank_mode is set to a non zero value in drirc.
2008-03-03 14:49:49 +08:00
612c22f131
Working revision.
2008-02-29 15:38:55 +01:00
2305100c0f
More post-ioctl work.
2008-02-29 13:25:55 +01:00
fd595fa4dc
Reinstate buffer idle before applying relocations.
2008-02-27 21:44:40 +01:00
72983ff301
Don't wait for buffer idle before applying relocations.
2008-02-27 19:46:28 +01:00
e87cec1968
[i915] Relocation fixes.
2008-02-26 10:47:05 +01:00
56bb29cf37
Make the execbuffer code reasonably safe against errors.
...
In particular -EAGAINs, which should be common during Xserver operation.
Also handle the fence creation failure case.
2008-02-26 00:05:26 +01:00
d6098db140
fix texture uploads with large 3d textures (bug 13980)
...
Texture uploads could hit the blitter coordinate limit, adjust the texture
offset when uploading the pieces. Make sure to check the end address of the
upload too.
2008-02-23 11:01:36 +01:00
0d32015974
nouveau: Remove some random (french) comment.
2008-02-22 19:28:54 +01:00
7e5f9c8bd3
nouveau: A single define of dma skips is more than enough.
2008-02-22 19:28:54 +01:00
b7086e6ae5
Fix one last occurance of struct _drm_i915_batchbuffer.
...
Thanks to Todd Merrill for pointing it out.
2008-02-22 11:22:52 -05:00
b0fee67a30
i915: Remove leading underscore from struct tags.
...
This matches the changes in mesa to use the system drm includes
for the definitions of the drm ioctl structs.
2008-02-22 00:12:39 -05:00
9d1061b8cf
fix SAREA
2008-02-20 22:23:31 +00:00
5d8c754bc2
[915]: more registers for S3 (DSPCLK_GATE_D, CACHE_MODE_0, MI_ARB_STATE)
...
Failing to preserve the MI_ARB_STATE register was causing FIFO underruns on
the VGA output on my HP 2510p after resume.
2008-02-16 20:14:49 -08:00
cd87e6352b
nouveau: no GART on ia64 either.
2008-02-16 03:50:29 +01:00
15cbde683f
nv40: actually init all tile regs.
2008-02-16 04:47:02 +11:00
373dbcf8b2
i915: Add a dri2 init path that gets the lock from the dri2 sarea.
2008-02-13 13:34:02 -05:00
db3f03ae35
i915: Only look up dev_priv->mmio_map if it's not already set up
2008-02-13 13:34:02 -05:00
ee15459483
i915: Add I915_PARAM_CHIPSET_ID param to get chipset ID.
2008-02-13 13:34:02 -05:00
4feb0638f1
i915: Make sarea_priv setup optional.
2008-02-13 13:34:02 -05:00
6f19473191
Fix saveGR array size
...
Make sure we have enough room for all the GR registers or we'll end up
clobbering the AR index register (which should actually be harmless
unless the BIOS is making an assumption about it).
2008-02-07 11:21:09 -08:00
8b6c96dedd
i915: save/restore interrupt state
...
On resume, if the interrupt state isn't restored correctly, we may end
up with a flood of unexpected or ill-timed interrupts, which could cause
the kernel to disable the interrupt or vblank events to happen at the
wrong time. So save/restore them properly.
2008-02-07 10:48:08 -08:00
76748efae2
i915: Re-report breadcrumbs on poll to the fence manager,
...
since a breadcrumb may actually turn up before a corresponding fence object
has been placed on the fence ring.
2008-02-05 10:36:49 +01:00
a0781e7622
nouveau: make nv34 work every time, not just every 2nd time
...
And make nv30_graph_init a bit more like mmio-traces
2008-02-04 16:38:31 +00:00
733e07663e
nouveau: NV40 can/should now be able to run after the blob.
...
- Moved the fix from the ddx to drm, because it seemed more appropriate.
- Don't be shy, report if it works for you or not.
2008-02-02 12:46:47 +01:00
47ee6237fe
i915: Avoid calling drm_fence_flush_old excessively.
2008-01-30 22:14:02 +01:00
f1edb7ad91
Simplify the fencing code and differentiate between flushes and
...
waiting types.
Add a "command_stream_barrier" method to the bo driver.
2008-01-30 22:06:02 +01:00
9a7e45858d
nv40: some more nv67 changes
...
With some luck the drm-side will be OK now for this chipset.
2008-01-30 11:50:17 +11:00
0744cb153a
Add new RV380 pci id
...
bug 14289
2008-01-29 10:11:27 -05:00
b8755ff7c3
drm: add initial rs690 support for drm.
...
This adds support for configuring the RS690 GART.
2008-01-27 12:50:31 +10:00
6bfb9b639a
mach64: fix after vblank-rework
...
don't disable vblank interrupts (similar to r128)
2008-01-25 16:54:29 +02:00
bfdddd218e
Fixup modeset ioctl number & typedef usage
...
Should be 0x08 rather than 0xa0, and shouldn't use typedefs.
2008-01-24 21:13:33 -08:00
e3c42f0004
Merge commit 'airlied/i915-ttm-cfu'
...
This requires updated Mesa to handle the new relocation format.
2008-01-24 12:44:19 -08:00
c7ee6cc269
Remove broken 'in vblank' accounting
...
We need to return an accurate vblank count to the callers of
->get_vblank_counter, and in the Intel case the actual frame count
register isn't udpated until the next active line is displayed, so we
need to return one more than the frame count register if we're currently
in a vblank period.
However, none of the various ways of doing this is working yet, so
disable the logic for now. This may result in a few missed events, but
should fix the hangs some people have seen due to the current code
tripping the wraparound logic in drm_update_vblank_count.
2008-01-24 08:57:04 -08:00
5b99306452
i915: fix missing header when copying data from userspace
2008-01-24 15:18:09 +10:00
34b71eb451
i915 make relocs use copy from user
...
Switch relocs to using copy from user and remove index and pass buffer
handles in instead.
2008-01-24 14:37:40 +10:00
b5a34f5da5
Fix thinko in get_vblank_counter
...
Should use vtotal not htotal to figure out if we're in a vblank period.
2008-01-23 08:39:57 -08:00
cb91784371
Fix IS_I915G macro
...
One to many parantheses...
2008-01-23 08:38:01 -08:00
7c726086dd
nouveau: Fix warning in nouveau_mem.c
2008-01-23 16:40:19 +01:00
2f19fe4498
drm/i915: add support for E7221
2008-01-23 16:44:51 +10:00
531f25cfe9
Correct vblank count value
...
The frame count registers don't increment until the start of the next
frame, so make sure we return an incremented count if called during the
actual vblank period.
2008-01-22 15:16:01 -08:00
893e311999
i915 irq fixes
...
Ack the IRQs correctly (PIPExSTAT first followed by IIR). Don't read
vblank counter registers on disabled pipes (might hang otherwise). And
deal with flipped pipe/plane mappings if present.
2008-01-22 13:11:29 -08:00
0cd4cbc9a6
Merge branch 'master' into vblank-rework, including mach64 support
...
Conflicts:
linux-core/drmP.h
linux-core/drm_drv.c
shared-core/i915_drv.h
shared-core/i915_irq.c
shared-core/mga_irq.c
shared-core/radeon_irq.c
shared-core/via_irq.c
Mostly trivial conflicts.
mach64 support from Mathieu Bérard.
2008-01-22 09:42:37 -08:00
5231a524f5
Revert "Fix pipe<->plane mapping vs. vblank handling (again)"
...
This reverts commit bfc29606e4
2008-01-22 14:42:48 +11:00
616cef5ec8
nouveau: don't forget NV80.
2008-01-21 21:11:47 +01:00
641c9a2ecc
nouveau: new card family for old card designs.
2008-01-21 21:01:28 +01:00
44a9fa8cc6
Add additional explanation of DRM_BO_FLAG_CACHED_MAPPED before I forget again.
2008-01-17 16:55:43 -08:00
ac6b3780c8
i915: Add chipset id for Intel Integrated Graphics Device
...
This adds new chipset id in drm.
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com>
2008-01-15 13:06:09 -05:00
88c511e49d
Properly propagate the user-space fence flags.
...
This avoids a sync flush when user-space has already programmed
and MI_FLUSH in the batchbuffer.
2008-01-15 10:03:41 +01:00
269d518008
nouveau: make mem alloc debug a little more verbose.
2008-01-14 03:16:42 +01:00
f0b7c45653
nv05: enable ctx/op methods, and ignore patch valid failures.
...
Yes, I'm quite aware "real" nv04 doesn't support this, hopefully the GPU
will just ignore those PGRAPH_DEBUG_3 bits on that hw.
2008-01-11 12:51:08 +11:00
5f15f317fb
nouveau: AGP reset correction - don't touch FW bit
2008-01-08 20:30:21 +00:00
0bfd09f719
nv50: more small changes
2008-01-07 18:56:44 +11:00
942b500e24
nv50: oops, lost some state saving along the way somewhere.
...
xf86-video-nv will now work again after nouveau.
2008-01-07 18:19:16 +11:00
3d248cd7e4
nv50: hook up timer funcs...
2008-01-07 17:23:31 +11:00
7a4ba7273c
nv50: abort on chips without ctx ucode
2008-01-07 17:13:22 +11:00
15f8fd34df
nv50: some needed ctx vals
2008-01-07 17:09:00 +11:00
3d3d509dca
nv50: some cleanups + small changes
2008-01-07 17:08:59 +11:00
cd19dcef4f
Nouveau: ppc oops.
2008-01-07 06:11:33 +01:00
de522ae742
Nouveau: move PPC bios copy to firstopen.
2008-01-07 05:54:37 +01:00
bd5d760a10
nouveau: Add ctx_voodoo for NV86
2008-01-06 10:09:47 -05:00
30fba69a68
via: add P4M900 pci id.
...
bug 12108
2008-01-04 16:29:04 +10:00
71adbfc874
[PATCH] nouveau: reset AGP on init for < nv40
...
This is necessary for AGP to work after running bios init scripts on nv3x, and
is seen in mmio traces of all cards (nv04-nv4x)
I'm not making the equivalent change to nv40_mc.c, as early cards (6200, 6800gt)
use the 0x000018XX PBUS and later cards use the 0x000880XX PBUS and I don't know
the effects of using the wrong one
2008-01-04 05:08:15 +01:00
381724a35b
[PATCH] nouveau: Fix nv20/30 context loading
...
Don't set the context as valid until it has been loaded
2008-01-04 05:07:35 +01:00
Oliver McFadden
Stuart Bennett
Dave Airlie
Ben Skeggs
Alex Deucher
Alex Deucher
Dave Airlie
Thomas Hellstrom
Alex Deucher
Keith Packard
Xiang, Haihao
Eric Anholt
Zou Nan hai
Roland Scheidegger
Maarten Maathuis
Kristian Høgsberg
Alan Hourihane
Stephane Marchesin
Jesse Barnes
Mirko
Maciej Cencora
George Sapountzis
Jesse Barnes
Zhenyu Wang
Jeremy Kolb
Xavier Bachelot