49075b678f
r500: add two more register ranges for mesa driver to setup
2008-05-23 09:40:26 +10:00
74a9ea896e
drm: fix nouveau warning
2008-05-23 09:40:26 +10:00
1cde3cc1ac
i915: check dummy page before freeing
...
The dummy read page will point to NULL if drm_bo_driver_init failed at
firstopen (modeset is not enabled), and will cause kernel oops at
subsequent drm_lastclose call, so be sure to check it.
2008-05-22 10:35:55 -07:00
e8320a716d
i915: init bo mm at driver init only when modeset=1
...
To avoid bo memory manager being inited twice, it will be called
at firstopen when modeset is not enabled.
2008-05-22 10:34:08 -07:00
d6f7968577
[gem] Replace ring throttling hack with actual time measurement.
2008-05-21 16:40:14 -07:00
54fa32cdfe
[gem] Fix bad test for list_for_each completion.
...
Since it's a circular list, the entry won't be NULL at termination.
2008-05-21 15:15:58 -07:00
7078978db0
[gem] Hold a reference on the object in i915_gem_wait_space.
...
Otherwise, in the middle of the function called using it the last ref
might disappear.
2008-05-21 15:04:07 -07:00
f8e38e49dd
[intel-gem] invalidate ring locals for pin/unpin/set_domain/free functions
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Ring locals must be reloaded from hardware in case the X server ran.
2008-05-21 15:00:16 -07:00
91c6c4b240
rs690/r500: vblank support.
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The new display controller has the vblank interrupts in a different place.
Add support for vbl interrupts for these chips
2008-05-21 21:27:33 +10:00
af8e087157
[gem] Use a separate sequence number field from classic/ttm
...
This lets us get some qualities we desire, such as using the full 32-bit
range (except zero), avoiding DRM_WAIT_ON, and a 1:1 mapping of active
sequence numbers to request structs, which will be used soon for throttling
and interrupt-driven list cleanup.
2008-05-20 14:16:26 -07:00
ab36a6f983
[gem] Rename sequence numbers from "cookie" to "seqno"
2008-05-20 10:53:10 -07:00
6c3ac484b0
[gem] Clean up active/inactive list handling using helper functions.
...
Additionally, a boolean active field is added to indicate which list an
object is on, rather than smashing last_rendering_cookie to 0 to show
inactive. This will help with flush-reduction later on, and makes the code
clearer.
2008-05-20 10:52:39 -07:00
8399656106
r500: add more register ranges for Mesa driver
2008-05-17 10:22:12 +10:00
7dced2f33a
[gem] Hold dev->struct_mutex to protect structure data.
2008-05-15 18:45:23 -07:00
3ab152da66
[gem] Rename the GTT LRU lists to active (executing) and inactive (idle).
2008-05-15 11:59:58 -07:00
aafafe507b
[gem] typo fix in comment.
2008-05-15 11:59:57 -07:00
a09c0bbe11
ati_pcigart: oops wrong way around not that it actually mattered
2008-05-14 22:48:12 +10:00
4c6ec02eb8
ati_pcigart: stop working in the evenings you mess up too often
2008-05-14 22:44:22 +10:00
2712cdeec3
Revert "ati_pcigart: fixup properly this version might even work"
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This reverts commit bc0836e12a
2008-05-14 22:43:28 +10:00
bc0836e12a
ati_pcigart: fixup properly this version might even work
2008-05-14 22:42:21 +10:00
dd1f33f83c
ati_pcigart: fill out 40-bit gart table support properly
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Thanks to Alex for supplying this info.
2008-05-14 22:35:32 +10:00
caace3692f
RS4xx: separate out RS400 and RS480 IGP chips
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RS400 (intel based IGP) and RS480 (AMD based IGP) have
different MC and GART setups. Currently we only support
RS480.
2008-05-13 21:02:17 -04:00
e4f29968f4
Merge branch 'modesetting-101' of ssh://git.freedesktop.org/git/mesa/drm into modesetting-101
2008-05-13 14:47:17 -07:00
ee631e1b86
i915: register definition & header file cleanup
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It would be nice if one day the DRM driver was the canonical source for
register definitions and core macros. To that end, this patch cleans
things up quite a bit, removing redundant definitions (some with
different names referring to the same register) and generally tidying up
the header file.
2008-05-13 14:44:17 -07:00
5be53a0881
i915: execbuf now works without i915_dma_init being called
2008-05-13 09:26:26 +02:00
d32ce7f621
i915: TV hotplug fixes
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In order to avoid recursive ->detect->interrupt->detect->interrupt->...
we need to disable TV hotplug interrupts in
intel_tv.c:intel_tv_detect_type. We also need to enable the TV interrupt
detection and hotplug sequence properly in i915_irq.c.
2008-05-12 15:47:19 -07:00
6e46a3c762
[GEM] Update testcases for new API.
2008-05-12 15:42:20 -07:00
f650d7240a
[GEM] Typo (and thinking) fixes in drm-gem.txt and doxygen.
2008-05-12 13:17:01 -07:00
17e8000ac0
[intel] Minor kludge -- wait for the ring to be nearly empty before queuing
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No need to fill the ring that much; wait for it to become nearly empty
before adding the execbuffer request. A better fix will involve scheduling
ring insertion in the irq handler.
2008-05-12 13:04:18 -07:00
7e7ea313c4
[intel] When polling for ring space, sleep for a lot longer (10ms)
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If the ring is full, the engine will surely be running for more than 10ms.
2008-05-12 13:03:16 -07:00
6aeff6b9e3
[gem] Set write domain to CPU when doing pwrite.
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Leave the flush call in place, which can fix domains up if necessary.
2008-05-12 13:01:57 -07:00
6950b7da71
[gem] Clarify use of explicit domain control. Remove Gen3 from I-cache usage.
2008-05-12 13:00:55 -07:00
a51e38548c
fix kernel oops when removing fb
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drm_crtc->fb may point to NULL, f.e X server will allocate a new fb
and assign it to the CRTC at startup, when X server exits, it will destroy
the allocated fb, making drm_crtc->fb points to NULL.
2008-05-12 12:31:56 -07:00
b2dee13f5d
free dummy read page if fail to init mm
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Since drm_bo_driver_init will be called in driver_load, we need to free
what it alloced when error to avoid memory leak.
2008-05-12 12:07:27 -07:00
f1b9bbe2b8
modeset init code cleanup
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moving modeset init code into one function and correct error
handling druing i915 init
2008-05-12 12:07:04 -07:00
af60d87869
fix G33 hardware status page in modeset
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We need to alloc a hw status page bo for G33 if modeset is enabled since the 2D
driver can't alloc gfx memory when working in drm modeset.
2008-05-12 12:04:02 -07:00
10d754f0a2
RADEON: fix copy/pasto in last commit
2008-05-12 14:49:43 -04:00
75bc739bee
R3/4/5: init pipe setup in drm
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Similar (broken) code in mesa needs to be removed
2008-05-12 09:44:20 -04:00
e16a7101e8
RADEON: cleanup radeon_do_engine_reset()
2008-05-12 09:35:06 -04:00
5532b8d2a0
R300+: fixup pixcache flush
2008-05-12 09:30:47 -04:00
3582e82f14
RS4xx: fix MCIND index mask
2008-05-12 09:24:13 -04:00
d26af273f8
RADEON: write AGP_BASE_2 on chips that support it
2008-05-12 09:21:45 -04:00
c307e50724
R300+: fixup PURGE/FLUSH macros
2008-05-12 09:18:28 -04:00
fb9eaff747
Radeon IGP: merge RS4xx/RS6xx gart setup
2008-05-12 09:13:44 -04:00
68b7f550ba
Radeon IGP: wrap MCIND access
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first step in merging rs4xx/rs6xx gart setup
2008-05-12 09:00:40 -04:00
a34025ce22
Radeon IGP: clean up registers and magic numbers
2008-05-12 08:56:11 -04:00
3f66a0005c
drm: remove root only from a lot of drm ioctls to get stuff running as non-root
2008-05-12 16:29:22 +10:00
1eedeed091
drm: masters are always authenticated
2008-05-12 16:28:58 +10:00
8f7fc880e8
drm: fix oops on reading proc file with no master
2008-05-12 16:28:40 +10:00
ff39db099b
[GEM] Make pread/pwrite manage memory domains. No luck with movnti though.
...
pread and pwrite must update the memory domains to ensure consistency with
the GPU. At some point, it should be possible to avoid clflush through this
path, but that isn't working for me.
2008-05-11 00:10:16 -07:00
Dave Airlie
Hong Liu
Eric Anholt
Keith Packard
Alex Deucher
Jesse Barnes
Jakob Bornecrantz