f524870184
nouveau: fix the build on big endian (thanks CyberFoxx)
2007-02-14 00:08:55 +01:00
17985f07d6
nouveau: more work on the nv04 context switch code.
2007-02-06 01:17:32 +01:00
8c663b4e56
nouveau: and of course, I was missing the last nv04 piece.
2007-02-03 06:13:27 +01:00
5a072f32c8
nouveau: rename registers to their proper names.
2007-02-03 04:57:06 +01:00
6d9ef1a960
nouveau: simplify and fix BIG_ENDIAN flags
2007-01-25 23:06:48 +01:00
ab72a7714e
nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching.
2007-01-18 21:40:21 -05:00
78a4f5c1bc
nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.
...
Hook into nv20 pgraph switching functions (they're identical for nv3x).
Actually call nv30_pgraph_context_init so the ctx_table is allocated.
Thanks to Carlos Martin for the help.
2007-01-17 08:46:59 -05:00
f04347f371
nouveau: nv20 graph ctx switch.
...
Untested...
2007-01-13 23:19:41 +01:00
cd5f543b2f
nouveau: first step to make graph ctx works
...
It is still not working, but now we could use some 3D commands
without needed to run nvidia blob before.
2007-01-13 21:44:50 +01:00
1bad7e0d02
nouveau : remove useless init : we clear RAMIN before
2007-01-12 20:31:18 +01:00
4297a83b48
nouveau: get nv30 context switching to work.
...
* Pulled in some registers from nv10reg.h. Needed for context switching.
* Filled in nv30 graphics context (based on nv40_graph.c).
* Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-12 00:14:54 -05:00
faa4612299
nouveau: avoid allocating vram that's used as instance memory.
2007-01-08 00:44:02 +11:00
0f95ddc428
Merge branch 'master' of git+ssh://matc@git.freedesktop.org/git/mesa/drm/
2007-01-05 19:41:12 +01:00
9d167f1f4b
Add basic pgraph context for nv10.
...
It only fake a context switch : pgraph state are not save/restored.
2007-01-05 19:40:11 +01:00
f80659bc29
Cleanup the nv04 fifo code a bit.
2007-01-05 19:37:06 +01:00
91855bb254
nouveau: oops, forgot to free RAMIN..
2007-01-02 16:35:00 +11:00
41da9fd2e5
nouveau: Hook up grctx code for NV4x.
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This is enough to get grctx switching going on my NV40 and C51 after
the binary driver has initialised the card first.
Bumping the drm patchlevel because the ddx needs some modifications to
have NV4x work at all with these changes.
2007-01-02 15:08:04 +11:00
2c3bc69ba2
nouveau: Only clobber PFIFO if no channels are already alloc'd
...
With this change the GPU is responsible for doing the channel switch
itself. This is needed for the upcoming NV4x PGRAPH context work as
we don't yet know enough to manually swap PGRAPH contexts.
2007-01-02 14:41:34 +11:00
9e019df757
nouveau: Alloc cmdbuf for each channel individually
2006-12-26 23:30:26 +11:00
b7586ab539
nouveau: save/restore endianness flag on FIFO switch
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This makes my G5 survive glxinfo and nouveau_demo - airlied
2006-12-21 17:47:10 +11:00
1a40f3318c
Port remaining NV4 RAMIN access from the ddx into the drm.
...
Should fix lockups seen on NV4 cards.
2006-12-12 00:11:42 +11:00
30acb90a60
Merge the pciid work.
...
Add getparams for AGP and FB physical adresses.
Fix the MEM_ALLOC issue properly.
Fix context switches for nv44.
Change the DRM version to 0.0.1.
2006-12-03 10:02:54 +01:00
80d75cf695
Use nouveau_mem.c to allocate RAMIN.
2006-11-30 10:31:42 +11:00
b1a9a76971
Wrap access to objects in RAMIN.
...
This will make it easier to support extra RAMIN in vram at a later point.
2006-11-30 08:35:42 +11:00
f48a7685bd
For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context.
...
When cleaning a fifo, we shouldn't assume everybody use nv40 ;)
Fill DMA_SUBROUTINE fill correct value.
2006-11-28 21:32:03 +01:00
9ac7a8b0b4
Only return FIFO number if the FIFO is marked as in use..
2006-11-18 10:09:29 +11:00
e9194dd1b0
Check some return vals, fixes a couple of oopses.
2006-11-18 10:03:45 +11:00
18bba3fa29
Dump some useful info when a PGRAPH error occurs.
...
The "channel" detect doesn't work on my nv40, but the rest
seems to produce sane info.
2006-11-17 08:05:23 +11:00
2fd812f8ef
Completely untested NV10/20/30 FIFO context switching changes.
2006-11-14 09:00:31 +11:00
7002082944
Restructure initialisation a bit.
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- Do important card init in firstopen
- Give each channel it's own cmdbuf dma object
- Move RAMHT config state to the same place as RAMRO/RAMFC
- Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-14 08:11:49 +11:00
9ef4bbc66c
Hack around yet another "X restart borkage without nouveau.ko reload" problem.
...
On X init, PFIFO and PGRAPH are reset to defaults. This causes the GPU to
loose the configuration done by the drm. Perhaps a CARD_INIT ioctl a proper
solution to having this problem again in the future..
2006-11-14 04:51:13 +11:00
2dd3c039fd
fixup fifo size so it is page aligned
2006-11-06 11:42:15 +11:00
b5cf0d635c
Remove hack which delays activation of a additional channel. The previously active channel's state is saved to RAMFC before PFIFO gets clobbered.
2006-10-18 02:37:19 +11:00
4b43ee63f9
NV40: *Now* fifo ctx switching works for me..
...
Ok, I lied before.. it was a fluke it worked and required magic to repeat it..
It actually helps to fill in RAMFC entries in the correct place.
The code also clears RAMIN entirely instead of just the hash-table.
2006-10-17 12:33:49 +11:00
98e718d48f
NV40: FIFO context switching now WorksForMe(tm)
2006-10-17 07:29:31 +11:00
1943f39d8c
Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup code a bit.
2006-10-17 06:37:40 +11:00
2c5b91aecf
Again more work on context switches. They work, sometimes. And when they do they seem to screw up the PGRAPH state.
2006-10-14 16:36:11 +02:00
3a0cd7c7e2
Add the missing breaks.
2006-10-14 01:21:31 +02:00
b509abe413
Fix the fifo context size on nv10, nv20 and nv30.
2006-10-13 22:35:22 +02:00
4988074794
Fix some randomness in activating a second channel on NV40 (odd GET/PUT vals). Ch 1 GET now advances, but no ctx_switch.
2006-10-14 06:57:49 +11:00
7ef44b2b8d
Still more work on the context switching code.
2006-10-12 17:31:49 +02:00
a749d9d5b4
More work on the context switch code. Still doesn't work. I'm mostly convinced it's an initialization issue.
2006-10-12 01:08:15 +02:00
dd473411f8
Context switching work.
...
Added preliminary support for context switches (triggers the interrupts, but hangs after the switch ; something's not quite right yet).
Removed the PFIFO_REINIT ioctl. I hope it's that a good idea...
Requires the upcoming commit to the DDX.
2006-10-11 00:28:15 +02:00
0ef29768ca
Fix second start of X server without module reload beforehand, and a couple of other fixes.
...
- Mark the correct RAMIN slots as free (oops)
- Remove a VRAM alloc that shouldn't have been there (oops)
- Move HT init out of firstopen() and into dma_init()
- Setup PFIFO_RAM{HT,FC,RO} in pfifo_init()
2006-09-07 23:59:19 +10:00
b119966ae6
Allow cmdbuf location(AGP,VRAM) and size to be configured.
2006-09-03 06:36:06 +10:00
24dddc2754
Add stub {get,set}param ioctls.
2006-08-30 16:55:02 +10:00
fef9b30a2b
initial import of nouveau code from nouveau CVS
2006-08-27 08:55:02 +10:00
Stephane Marchesin
Patrice Mandin
Jeremy Kolb
Matthieu Castet
Ben Skeggs
Ben Skeggs
Dave Airlie
Dave Airlie