This is the new ioctl wrapper used by the new admgpu driver.
It's primarily used by xf86-video-amdgpu and mesa.
v2: fix amdgpu_drm.h install
v3: Integrate some of the sugestions from Emil:
clean up Makefile.am, configure.ac
capitalize header guards
fix _FILE_OFFSET_BITS with config.h
use drm_mmap/drm_munmap
Remove unused ARRAY_SIZE macro
use shared list implementation
use shared math implementation
use drmGetNodeTypeFromFd helper
v4: remove unused tiling defines
v5: include amdgpu.h in Makefile.am
v6: update amdgpu_drm.h
v7: libdrm.h -> libdrm_macros.h
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Add support for the atomic modesetting ioctl through a property-set API.
v1: Squashed intermediate patches from Ville, Rob and myself. Updated
for current kernel interface (no blobs).
v2: Rewrite user-facing API to provide transactional/cursor interface.
Use memclear to zero out ioctl.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Signed-off-by: Daniel Stone <daniels@collabora.com>
v3 [Emil Velikov]: Remove DRM_CAP_ATOMIC - superseded by
DRM_CLIENT_CAP_ATOMIC.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Add a flag allowing Nouveau to specify that an object should be coherent
at allocation time. This is required for some class of objects like
fences which are randomly-accessed by both the CPU and GPU. This flag
instructs the kernel driver to make sure the object remains coherent
even on architectures for which coherency is not guaranteed by the bus.
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
The main incentive to do this is to get I915_PARAM_REVISION.
v2: Rebase on top of some changes that were made to the header without
copying the whole file from the kernel source.
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Neil Roberts <neil@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Update kernel interface with new I915_GETPARAM ioctl entries for
subslice total and EU total. Add a wrapping function for each
parameter. Userspace drivers need these values when constructing
GPGPU commands. This kernel query method is intended to replace
the PCI ID-based tables that userspace drivers currently maintain.
The kernel driver can employ fuse register reads as needed to
ensure the most accurate determination of GT config attributes.
This first became important with Cherryview in which the config
could differ between devices with the same PCI ID.
The kernel detection of these values is device-specific. Userspace
drivers should continue to maintain ID-based tables for older
devices which return ENODEV when using this query.
v2: remove unnecessary include of <stdbool.h> and increment the
I915_GETPARAM indices to match updated kernel patch.
For: VIZ-4636
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Update drm_mode.h defines from kernel upstream for connector and
encoder types to expose DSI and other newly defined types.
Signed-off-by: Adam Cheney <acheney@nvidia.com>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
The DRM_TEGRA_GEM_SET_FLAGS IOCTL can be used to set the flags of a
buffer object after it has been allocated or imported. Flags associated
with a buffer object can be queried using the DRM_TEGRA_GEM_GET_FLAGS
IOCTL.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Currently the tiling parameters of buffer objects can only be set at
allocation time, and only a single tiled mode is supported. This new
DRM_TEGRA_GEM_SET_TILING IOCTL allows more modes to be set and also
allows the tiling mode to be changed after the allocation. This will
enable the Tegra DRM driver to import buffers from a GPU and directly
scan them out by configuring the display controller appropriately.
To complement this, the DRM_TEGRA_GEM_GET_TILING IOCTL can query the
current tiling mode of a buffer object. This is necessary when importing
buffers via handle (as is done in Mesa for example) so that userspace
can determine the proper parameters for the 2D or 3D engines.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the libdrm_tegra helper library to encapsulate Tegra-specific
interfaces to the DRM.
Furthermore, Tegra is added to the list of supported chips in the
modetest and vbltest programs.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Both of these headers are not installed since they were imported.
They are not even used internally. The latter no longer exist in the
kernel...
Note the * symbol in EXTRA_DIST causes 'make distcheck' to fail. When
was the last time we ran it ?
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Rather than having two extra makefiles in order to ship ~10 headers
just fold its 5 lines of code into the top one makefile.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Will be used to consolidate the required sources lists as well as the
install-able headers. This is turn will help us to avoid the
duplication with the upcoming Android build support.
v2: Rename the headers variable to *_H_FILES.
v3: Rebase on top of symbol visibility patches.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Use "drm.h" instead of "drm/drm.h" as used in the other header files.
Fixes xserver-xorg-video-qxl build with KMS support on Debian, where this
file is installed in /usr/include/libdrm.
Fixes Debian bug #746807
Reported-by: Bastian Blank <waldi@debian.org>
Signed-off-by: Andreas Boll <andreas.boll.dev@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Bug fixes and simplification by Marek.
We have to use the tile index of 0 for non-MSAA depth-stencil after all.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
I would have just used the drmIoctl interface directly in Mesa, but the
ioctl needs some data from the drm_intel_context that is not exposed
outside libdrm.
This ioctl is in the drm-intel-next tree as b635991.
v2: Update based on Mika's kernel work.
v3: Fix compile failures from last-minute typos. Sigh.
v4: Import the actual changes from the kernel i915_drm.h. Only comments
on some fields of drm_i915_reset_stats differed. There are still some
deltas between the kernel i915_drm.h and the one in libdrm, but those
can be resolved in other patches.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v3]
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
This reverts commit 6335e1d28c.
No taxation without representation, in other words no userspace without kernel
stuff being in a stable location, either drm-next but I'll accept drm-intel-next
for intel specific stuff.
I would have just used the drmIoctl interface directly in Mesa, but the
ioctl needs some data from the drm_intel_context that is not exposed
outside libdrm.
v2: Update based on Mika's kernel work.
v3: Fix compile failures from last-minute typos. Sigh.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
This exposes the kernel API for performing asynchronous flips
Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
The following minor changes were needed to these headers:
* Convert // comments to /* */
* No , after final member of enum
With these changes, these header files can be included by a program that
is built with gcc options:
-std=c89 -Werror -pedantic
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
These are just basic ioctl wrappers around the prime ioctls,
along with the capability reporting.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This just moves over some missing caps from the kernel.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
A bitmask property is similar to an enum. The enum value is a bit
position (0-63), and valid property values consist of a mask of
zero or more of (1 << enum_val[n]).
Signed-off-by: Rob Clark <rob@ti.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
make headers_install in kernel. Copy to here.
v2: signed ns_timeout
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Sync drm.h with from kernel headers for the new PRIME_HANDLE_TO_FD
and PRIME_FD_TO_HANDLE ioctls from Dave Airlie's "drm: base prime/
dma-buf support (v5)" kernel patch.
Signed-off-by: Rob Clark <rob@ti.com>
The surface allocator is able to build complete miptree when allocating
surface for r600/r700/evergreen/northern islands GPU family. It also
compute bo size and alignment for render buffer, depth buffer and
scanout buffer.
v2 fix r6xx/r7xx 2D tiling width align computation
v3 add tile split support and fix 1d texture alignment
v4 rework to more properly support compressed format, split surface pixel
size and surface element size in separate fields
v5 support texture array (still issue on r6xx)
v6 split surface value computation and mipmap tree building, rework eg
and newer computation
v7 add a check for tile split and 2d tiled
v8 initialize mode value before testing it in all case, reenable
2D macro tile mode on r6xx for cubemap and array. Fix cubemap
to force array size to the number of face.
v9 fix handling of stencil buffer on evergreen
v10 on evergreen depth buffer need to have enough room for a stencil
buffer just after depth one
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
This adds support for querying the kernel about the LLC support in the
hardware.
In case the ioctl fails, we assume that it is present on GEN6 and GEN7.
v2: fix the return code checking
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Add structs and functions necessary for the new plane and fb handling code,
including a new header, drm_fourcc.h, that includes the surface formats
supported by various DRM drivers.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Hi Alex,
Enclosed is a revised version of the patch sent on Mar 18, against
the master branch of the drm userspace (i.e. libdrm). Details
summarised in this thread:
http://lists.freedesktop.org/archives/dri-devel/2011-March/009499.html
This patch reconciles libdrm with the the kernel change that Dave
pushed this morning. It *supersedes* the previously sent patch (i.e.
apply it to the master branch as it exists at the time of this writing,
not as an incremental patch to the one sent previously).
Regards,
Ilija
Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
The kernel has always allowed userspace to underallocate objects
supplied for fencing. However, the kernel only allocated the object size
for the fence in the GTT and so caused tiling corruption. More recently
the kernel does allocate the full fence region in the GTT for an
under-sized object and so advertises that clients may finally make use
of this feature. The biggest benefit is for texture-heavy GL games on
i945 such as World of Padman which go from needing over 1GiB of RAM to
play to fitting in the GTT!
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This introduces a new API to exec on BSD ring buffer, for H.264 VLD
decoding.
Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com>
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
This patch to libdrm adds support for the new execbuf2 ioctl. If
detected, it will be used instead of the old ioctl. By using the new
drm_intel_bufmgr_gem_enable_fenced_relocs(), you can indicate that any
time a fence register is actually required for a relocation target you
will call drm_intel_bo_emit_reloc_fence instead of
drm_intel_bo_emit_reloc, which will reduce fence register pressure.
Signed-off-by: Eric Anholt <eric@anholt.net>
This commit encompasses the changes necessary to run on top of the 0.0.16
nouveau interface, additional APIs to support the new features of the
interface, as well as code from Luca Barbieri to improve the pushbuf
interface, which just happens to break nouveau's libdrm ABI so was delayed
until now.
API changes as a result of 0.0.16 DRM interface:
1. No more bo_pin()/bo_unpin(), these were only there for UMS and we no
longer support it.
2. Any random nouveau_bo can be submitted to the GPU as a push buffer.
3. Relocations can be applied on any nouveau_bo
This patch changes the pushbuffer ABI to:
1. No longer use/expose nouveau_pushbuffer. Everything is directly
in nouveau_channel. This saves the extra "pushbuf" pointer dereference.
2. Use cur/end pointers instead of tracking the remaining size.
Pushing data now only needs to alter cur and not both cur and remaining.
The goal is to make the *_RING macros faster and make the interface simpler
and cleaner in the process.
The *_RING APIs are unchanged, but those are inlined and the ABI is changed.
Also, anything accessing pushbuf->remaining instead of using AVAIL_RING
will need to be fixed.
The nouveau_drmif.h is not the Nouveau DRM kernel ABI file, but purely
user space stuff. Remove it, it does not belong in include/drm/.
Copy the right header from Nouveau kernel v2.6.31-rc9-757-gaca551c.
Signed-off-by: Pekka Paalanen <pq@iki.fi>
Jammy Zhou
Alex Deucher
Daniel Stone
Ville Syrjälä
Alexandre Courbot
Neil Roberts
Jeff McGee
Adam Cheney
Thierry Reding
Thierry Reding
Rob Clark
Emil Velikov
Andreas Boll
Tvrtko Ursulin
Damien Lespiau
Matt Roper
Marek Olšák
Ben Widawsky
Ian Romanick
Dave Airlie
Keith Packard
Daniel Kurtz
Michel Dänzer
Imre Deak
Xiang, Haihao
Jerome Glisse
Eric Anholt
Dave Airlie
Ben Widawsky
Rob Clark
Paulo Zanoni
Alan Coopersmith
Eugeni Dodonov
Jesse Barnes
Ilija Hadzic
Ben Skeggs
Chris Wilson
Francisco Jerez
Zou Nan hai
Kristian Høgsberg
Julien Cristau
Jakob Bornecrantz
Marek Olšák
Luca Barbieri
Marcin Kościelnicki
Robert Noland
Pekka Paalanen