2015-04-20 10:15:23 -06:00
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _AMDGPU_TEST_H_
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#define _AMDGPU_TEST_H_
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#include "amdgpu.h"
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2015-07-13 06:57:44 -06:00
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#include "amdgpu_drm.h"
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2015-04-20 10:15:23 -06:00
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/**
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* Define max. number of card in system which we are able to handle
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*/
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#define MAX_CARDS_SUPPORTED 4
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/* Forward reference for array to keep "drm" handles */
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extern int drm_amdgpu[MAX_CARDS_SUPPORTED];
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2017-01-24 15:29:52 -07:00
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/* Global variables */
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extern int open_render_node;
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2015-04-20 10:15:23 -06:00
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/************************* Basic test suite ********************************/
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/*
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* Define basic test suite to serve as the starting point for future testing
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*/
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/**
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* Initialize basic test suite
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*/
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int suite_basic_tests_init();
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/**
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* Deinitialize basic test suite
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*/
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int suite_basic_tests_clean();
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/**
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* Tests in basic test suite
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*/
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extern CU_TestInfo basic_tests[];
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/**
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* Initialize bo test suite
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*/
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int suite_bo_tests_init();
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/**
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* Deinitialize bo test suite
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*/
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int suite_bo_tests_clean();
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/**
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* Tests in bo test suite
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*/
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extern CU_TestInfo bo_tests[];
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/**
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* Initialize cs test suite
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*/
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int suite_cs_tests_init();
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/**
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* Deinitialize cs test suite
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*/
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int suite_cs_tests_clean();
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/**
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* Tests in cs test suite
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*/
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extern CU_TestInfo cs_tests[];
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2015-05-19 10:51:15 -06:00
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/**
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* Initialize vce test suite
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*/
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int suite_vce_tests_init();
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/**
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* Deinitialize vce test suite
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*/
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int suite_vce_tests_clean();
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/**
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* Tests in vce test suite
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*/
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extern CU_TestInfo vce_tests[];
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2017-04-03 13:52:31 -06:00
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/**
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+ * Initialize vcn test suite
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+ */
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int suite_vcn_tests_init();
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/**
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+ * Deinitialize vcn test suite
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+ */
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int suite_vcn_tests_clean();
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/**
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+ * Tests in vcn test suite
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+ */
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extern CU_TestInfo vcn_tests[];
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2017-08-15 09:33:43 -06:00
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/**
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* Initialize uvd enc test suite
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*/
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int suite_uvd_enc_tests_init();
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/**
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* Deinitialize uvd enc test suite
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*/
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int suite_uvd_enc_tests_clean();
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/**
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* Tests in uvd enc test suite
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*/
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extern CU_TestInfo uvd_enc_tests[];
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2017-10-02 12:07:48 -06:00
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/**
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* Initialize deadlock test suite
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*/
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int suite_deadlock_tests_init();
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/**
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* Deinitialize deadlock test suite
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*/
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int suite_deadlock_tests_clean();
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/**
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* Tests in uvd enc test suite
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*/
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extern CU_TestInfo deadlock_tests[];
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2017-10-27 09:09:11 -06:00
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/**
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* Initialize vm test suite
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*/
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int suite_vm_tests_init();
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/**
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* Deinitialize deadlock test suite
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*/
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int suite_vm_tests_clean();
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/**
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* Tests in vm test suite
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*/
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extern CU_TestInfo vm_tests[];
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2015-04-20 10:15:23 -06:00
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/**
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* Helper functions
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*/
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static inline amdgpu_bo_handle gpu_mem_alloc(
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amdgpu_device_handle device_handle,
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uint64_t size,
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uint64_t alignment,
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uint32_t type,
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uint64_t flags,
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2015-07-13 06:57:44 -06:00
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uint64_t *vmc_addr,
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amdgpu_va_handle *va_handle)
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2015-04-20 10:15:23 -06:00
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{
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struct amdgpu_bo_alloc_request req = {0};
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2015-07-13 06:57:44 -06:00
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amdgpu_bo_handle buf_handle;
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2015-04-20 10:15:23 -06:00
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int r;
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CU_ASSERT_NOT_EQUAL(vmc_addr, NULL);
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req.alloc_size = size;
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req.phys_alignment = alignment;
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req.preferred_heap = type;
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req.flags = flags;
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2015-07-13 06:57:44 -06:00
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r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
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2015-04-20 10:15:23 -06:00
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CU_ASSERT_EQUAL(r, 0);
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2015-07-13 06:57:44 -06:00
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r = amdgpu_va_range_alloc(device_handle,
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amdgpu_gpu_va_range_general,
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size, alignment, 0, vmc_addr,
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va_handle, 0);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_va_op(buf_handle, 0, size, *vmc_addr, 0, AMDGPU_VA_OP_MAP);
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CU_ASSERT_EQUAL(r, 0);
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return buf_handle;
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}
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static inline int gpu_mem_free(amdgpu_bo_handle bo,
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amdgpu_va_handle va_handle,
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uint64_t vmc_addr,
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uint64_t size)
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{
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int r;
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r = amdgpu_bo_va_op(bo, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_va_range_free(va_handle);
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CU_ASSERT_EQUAL(r, 0);
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r = amdgpu_bo_free(bo);
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CU_ASSERT_EQUAL(r, 0);
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return 0;
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2015-04-20 10:15:23 -06:00
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}
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2015-06-01 06:12:10 -06:00
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static inline int
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amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size,
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unsigned alignment, unsigned heap, uint64_t flags,
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2015-07-13 06:57:44 -06:00
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amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address,
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amdgpu_va_handle *va_handle)
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2015-06-01 06:12:10 -06:00
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{
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struct amdgpu_bo_alloc_request request = {};
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2015-07-13 06:57:44 -06:00
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amdgpu_bo_handle buf_handle;
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amdgpu_va_handle handle;
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uint64_t vmc_addr;
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2015-06-01 06:12:10 -06:00
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int r;
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request.alloc_size = size;
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request.phys_alignment = alignment;
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request.preferred_heap = heap;
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request.flags = flags;
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2015-07-13 06:57:44 -06:00
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r = amdgpu_bo_alloc(dev, &request, &buf_handle);
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2015-06-01 06:12:10 -06:00
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if (r)
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return r;
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2015-07-13 06:57:44 -06:00
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r = amdgpu_va_range_alloc(dev,
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amdgpu_gpu_va_range_general,
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size, alignment, 0, &vmc_addr,
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&handle, 0);
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if (r)
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goto error_va_alloc;
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r = amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_MAP);
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if (r)
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goto error_va_map;
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r = amdgpu_bo_cpu_map(buf_handle, cpu);
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if (r)
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goto error_cpu_map;
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*bo = buf_handle;
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*mc_address = vmc_addr;
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*va_handle = handle;
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return 0;
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error_cpu_map:
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2015-07-21 02:51:27 -06:00
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amdgpu_bo_cpu_unmap(buf_handle);
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2015-07-13 06:57:44 -06:00
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error_va_map:
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2015-07-21 02:51:27 -06:00
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amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
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2015-07-13 06:57:44 -06:00
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error_va_alloc:
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2015-07-21 02:51:27 -06:00
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amdgpu_bo_free(buf_handle);
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2015-07-13 06:57:44 -06:00
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return r;
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}
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static inline int
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amdgpu_bo_unmap_and_free(amdgpu_bo_handle bo, amdgpu_va_handle va_handle,
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uint64_t mc_addr, uint64_t size)
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{
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amdgpu_bo_cpu_unmap(bo);
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amdgpu_bo_va_op(bo, 0, size, mc_addr, 0, AMDGPU_VA_OP_UNMAP);
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amdgpu_va_range_free(va_handle);
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amdgpu_bo_free(bo);
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2015-06-01 06:12:10 -06:00
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return 0;
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2015-07-13 06:57:44 -06:00
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2015-06-01 06:12:10 -06:00
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}
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2015-06-02 05:05:41 -06:00
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static inline int
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amdgpu_get_bo_list(amdgpu_device_handle dev, amdgpu_bo_handle bo1,
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amdgpu_bo_handle bo2, amdgpu_bo_list_handle *list)
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{
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amdgpu_bo_handle resources[] = {bo1, bo2};
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return amdgpu_bo_list_create(dev, bo2 ? 2 : 1, resources, NULL, list);
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}
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2017-11-09 21:30:00 -07:00
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static inline CU_ErrorCode amdgpu_set_suite_active(const char *suit_name,
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CU_BOOL active)
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{
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CU_ErrorCode r = CU_set_suite_active(CU_get_suite(suit_name), active);
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if (r != CUE_SUCCESS)
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fprintf(stderr, "Failed to obtain suite %s\n", suit_name);
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return r;
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}
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static inline CU_ErrorCode amdgpu_set_test_active(const char *suit_name,
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const char *test_name, CU_BOOL active)
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{
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CU_ErrorCode r;
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CU_pSuite pSuite = CU_get_suite(suit_name);
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if (!pSuite) {
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fprintf(stderr, "Failed to obtain suite %s\n",
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suit_name);
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return CUE_NOSUITE;
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}
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r = CU_set_test_active(CU_get_test(pSuite, test_name), active);
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if (r != CUE_SUCCESS)
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fprintf(stderr, "Failed to obtain test %s\n", test_name);
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return r;
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}
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2015-04-20 10:15:23 -06:00
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#endif /* #ifdef _AMDGPU_TEST_H_ */
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