223061e084
nouveau : set the correct PGRAPH_CTX_CONTROL register
...
"5a072f32 (Stephane Marchesin 2007-02-03 04:57:06 +0100" broke nv10 ctx switch by setting wrong PGRAPH_CTX_CONTROL reg
2007-04-01 00:44:11 +02:00
ddb1715e06
Merge branch 'crestline-qa', adding support for the 965GM chipset.
2007-03-30 13:11:39 -07:00
bdabc8f998
nouveau: fix nv04 context switches.
2007-03-29 00:54:18 +02:00
81b811da37
drm/i915: set the bo up at firstopen time not after DMA init
...
This is required to use TTM to allocate the ring buffer.
2007-03-27 18:01:31 +10:00
406a894e52
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-27 12:53:13 +08:00
674cefd4fe
nouveau: move card initialisation into the drm
...
The PGRAPH init for the various cards will need cleaning up at some point,
a lot of the values written there are per-context state left over from the
all the hardcoding done in the ddx.
It's possible some cards get broken by this commit, let me know.
Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 20:59:37 +10:00
e7cd5a1e2d
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-23 17:00:41 +08:00
4988fa4886
nouveau: rework nouveau_fifo_alloc() so the drm can create internal FIFOs
2007-03-23 15:25:37 +11:00
2bb9de96d5
nouveau: remove unused cruft
2007-03-23 13:45:29 +11:00
0467ad4118
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-21 17:00:43 +08:00
e22225416a
nouveau: support multiple channels per client (breaks drm interface)
2007-03-21 17:57:47 +11:00
8398b99d8d
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-19 17:00:31 +08:00
26aba875e1
more whitespace issues
2007-03-19 08:56:24 +11:00
2463b03cb4
whitespace cleanup pending a kernel merge
2007-03-19 08:23:43 +11:00
df73975980
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-14 17:00:27 +08:00
93f66af76a
r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; not
...
enough information is known about them to be sure as to what the values mean.
2007-03-13 14:48:01 +00:00
80d0018bc0
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-13 17:00:31 +08:00
a90c2854a7
Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.
...
Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these
values are really unknown; ideally more reverse engineering should be done to
determine what these values mean and when they should be set.
2007-03-13 06:25:04 +00:00
90f8c691a5
nouveau: make sure cmdbuf object gets destroyed
2007-03-13 14:55:54 +11:00
1775202cf9
nouveau: associate all created objects with a channel + cleanups
2007-03-13 14:55:54 +11:00
7e2bbe2954
nouveau: s/fifo/channel/
2007-03-13 14:55:54 +11:00
462a6ea4ca
Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to either
...
R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values.
2007-03-13 01:19:56 +00:00
5667396e05
Guess another unknown register used for R300 pacification.
2007-03-13 00:50:05 +00:00
ab75d50d6c
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-12 09:03:40 +08:00
0cd5c650d1
nouveau: PUT,GET, not 2xPUT
2007-03-11 14:02:40 +01:00
b369724077
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-07 16:01:50 -05:00
6ffe94f008
Add via CX700.
2007-03-07 09:19:57 +01:00
0a85c9fa02
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-05 09:01:45 -05:00
188a93c9df
radeon: make PCI GART aperture size variable, but making table size variable
...
This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0
2007-03-04 19:10:46 +11:00
c9178c3d01
ati: make pcigart code able to handle variable size PCI GART aperture
...
This code doesn't enable a variable aperture it just modifies the codebase
to allow me fix it up later
2007-03-04 18:16:29 +11:00
6c48b8e7ff
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-03-01 09:02:09 -05:00
72caa48c82
nouveau: intrusive drm interface changes
...
graphics objects:
- No longer takes flags/dmaobj parameters, requires some major changes
to the ddx to setup the object through the FIFO. This change is
likely to cause breakages on some cards (tested on NV05,NV28,NV35,
NV40 and NV4E).
dma objects:
- now takes a "class" parameter, not really used yet but we may need
it at some point.
- parameters are checked, so clients can't randomly create DMA objects
pointing at whatever they feel like.
misc:
- Added FB_SIZE/AGP_SIZE getparams
- Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR
- Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't
NOTIFICATION_PENDING.
2007-02-28 15:41:53 +11:00
df2fc3ec62
Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline
2007-02-25 17:06:13 -08:00
9d8ba2d0d4
drm: remove unnecessary NULL checks, and fix some indents..
2007-02-25 10:48:26 +11:00
e0f53e59be
Simple fence object sample driver for via, based on idling the GPU.
...
Buffer object driver for via.
Some changes to buffer object driver callbacks.
Improve fence flushing.
2007-02-16 20:22:24 +01:00
7766378d97
Initial support for fence object classes.
...
(Fence objects belonging to different command submission mechanisms).
2007-02-15 12:11:38 +01:00
a78f70faad
Merge branch 'ttm-vram-0-1-branch'
2007-02-14 15:33:40 +01:00
5c9a7b0f94
Remove an intel-specific hack and replace it with a fence driver callback.
2007-02-14 13:31:35 +01:00
f524870184
nouveau: fix the build on big endian (thanks CyberFoxx)
2007-02-14 00:08:55 +01:00
59af900e4f
nouveau: fix memory initialization with multiple cards.
2007-02-14 00:07:31 +01:00
e1460426b8
Bugzilla Bug #9457
...
Add refcounting of user waiters to the DRM hardware lock, so that we can use the
DRM_LOCK_CONT flag more conservatively.
Also add a kernel waiter refcount that if nonzero transfers the lock for the kernel context,
when it is released. This is useful when waiting for idle and can be used
for very simple fence object driver implementations for the new memory manager.
It also resolves the AIGLX startup deadlock for the sis and the via drivers.
i810, i830 still require that the hardware lock is really taken so the deadlock remains
for those two. I'm not sure about ffb. Anyone familiar with that code?
2007-02-13 20:47:30 +01:00
80095ffe01
i915: Add 965GM pci id update
2007-02-13 16:20:45 +08:00
abc14ddfb5
Update flags and comments.
2007-02-12 21:40:42 +01:00
130c39be3c
Sync r300_reg.h from mesa driver. #10210
2007-02-11 10:24:14 +02:00
4f795a05f1
Merge branch 'i915-pageflip'
2007-03-10 00:11:10 +01:00
d734992e6a
i915: Only wait for pending flips before asynchronous flips again.
2007-03-10 00:10:49 +01:00
0741064df4
i915: Do not wait for pending flips on both pipes at the same time.
...
The MI_WAIT_FOR_EVENT instruction does not support waiting for several events
at once, so this should fix the lockups with page flipping when both pipes are
enabled.
2007-03-09 16:39:13 +01:00
1b3a6d4775
nouveau: remove a hack that's not needed since the last interface change.
2007-03-07 21:17:45 +11:00
5bd0e52dba
nouveau: ack PFIFO interrupts at PFIFO, not PMC.
2007-03-07 21:00:55 +11:00
a33859184a
i915: Eliminate dev_priv->current_page.
...
Always use dev_priv->sarea_priv->pf_current_page directly. This allows clients
to modify it as well while they hold the HW lock, e.g. in order to sync pages
between pipes.
2007-02-28 17:48:56 +01:00
074e10b384
i915: Only clean up page flipping when the last client goes away, not any one.
2007-02-28 15:57:08 +01:00
1cdc1b6fba
i915: Don't emit waits for pending flips before emitting synchronous flips.
...
The assumption is that synchronous flips are not isolated usually, and waiting
for all of them could result in stalling the pipeline for long periods of time.
Also use i915_emit_mi_flush() instead of an old-fashioned way to achieve the
same effect.
2007-02-28 15:23:19 +01:00
fd0fed3f1e
i915: Fix test for synchronous flip affecting both pipes.
2007-02-28 12:33:56 +01:00
1a0d890a42
i915: Add support for scheduled buffer swaps to be done as flips.
...
Unfortunately, emitting asynchronous flips during vertical blank results in
tearing. So we have to wait for the previous vertical blank and emit a
synchronous flip.
2007-02-22 17:21:18 +01:00
5a40c043cc
Add DRM_VBLANK_FLIP.
...
Used to request that a scheduled buffer swap be done as a flip instead of a
blit.
2007-02-22 17:19:30 +01:00
6f89584e13
i915: Improved page flipping support, including triple buffering.
...
Pages are tracked independently on each pipe.
Bump the minor version for 3D clients to know page flipping is usable, and
bump driver date.
2007-02-19 15:08:40 +01:00
34aa3393d0
i915: Page flipping enhancements.
...
Leave it to the client to wait for the flip to complete when necessary,
but wait for a previous flip to complete before emitting another one. This
should help avoid unnecessary stalling of the ring due to pending flips.
Call i915_do_cleanup_pageflip() unconditionally in preclose.
2007-02-19 15:08:40 +01:00
078e430726
i915: Unify breadcrumb emission.
2007-02-19 15:08:40 +01:00
53aee3122a
I915 accelerated blit copy functional.
...
Fixed - to System memory copies are implemented by
flipping in a cache-coherent TTM,
blitting to it, and then flipping it out.
2007-02-09 16:36:53 +01:00
898aca1a66
Warning fix: correct type of i915_mmio argument.
2007-02-07 21:26:02 -08:00
ef9a9d3cd1
Define __iomem for systems without it.
2007-02-07 21:26:01 -08:00
8918748058
Add chip family flags to i915 driver, and fix a missing '"' in mach64 ID list.
2007-02-07 21:26:01 -08:00
c1fbd8a566
Checkpoint commit.
...
Flag handling and memory type selection cleanup.
glxgears won't start.
2007-02-07 17:25:13 +01:00
609e3b0375
Implement a policy for selecting memory types.
2007-02-06 14:20:33 +01:00
17985f07d6
nouveau: more work on the nv04 context switch code.
2007-02-06 01:17:32 +01:00
8c663b4e56
nouveau: and of course, I was missing the last nv04 piece.
2007-02-03 06:13:27 +01:00
0c13657c33
nouveau: plugin the nv04 graph init function.
2007-02-03 06:00:29 +01:00
7ab9e7f36f
nouveau: cleanup the nv04 pgraph save/restore mechanism.
2007-02-03 05:56:42 +01:00
d69902db3b
nouveau: fix nv04 graph routines for new register names.
2007-02-03 05:25:36 +01:00
5a072f32c8
nouveau: rename registers to their proper names.
2007-02-03 04:57:06 +01:00
e64dbef911
nouveau: add NV04 registers required for PGRAPH context switching.
2007-02-03 04:23:09 +01:00
55f7859a25
nouveau: nv ctx switch opps the size of array was wrong
2007-02-02 23:01:03 +01:00
63cf3b3da7
nouveau: nv10 ctx switch, some regs are nv17+ only
2007-02-02 20:08:33 +01:00
6c04185857
via: Try to improve command-buffer chaining.
...
Bump driver date and patchlevel.
2007-02-02 09:22:30 +01:00
70bba11bc7
Disable AGP DMA for chips with the new 3D engine.
2007-02-02 09:22:15 +01:00
3024f23c65
memory manager: Make device driver aware of different memory types.
...
Memory types are either fixed (on-card or pre-bound AGP) or not fixed
(dynamically bound) to an aperture. They also carry information about:
1) Whether they can be mapped cached.
2) Whether they are at all mappable.
3) Whether they need an ioremap to be accessible from kernel space.
In this way VRAM memory and, for example, pre-bound AGP appear
identical to the memory manager.
This also makes support for unmappable VRAM simple to implement.
2007-01-31 14:50:57 +01:00
ee4ac5c897
nouveau: determine chipset type at startup, instead of every time we use it.
2007-01-28 23:48:33 +11:00
c744bfde2d
make works ctx switch on nv10.
2007-01-26 21:57:44 +01:00
9c03ca81e7
nouveau: oops, wrong indexing in nv17 regs
2007-01-26 21:05:59 +01:00
5534c90ff3
nouveau: read gpu type once
2007-01-26 19:54:35 +01:00
05d3ed472e
nouveau: only save/restore nv17 regs on nv17,18 hw
2007-01-26 19:25:49 +01:00
e7ba15a003
nouveau: add extra pgraph registers
2007-01-26 19:24:34 +01:00
d4c9f135b5
nouveau: add some nv10 pgraph defines
2007-01-26 18:10:31 +01:00
6d9ef1a960
nouveau: simplify and fix BIG_ENDIAN flags
2007-01-25 23:06:48 +01:00
90ae39d2f0
nouveau: nv4c default context
2007-01-25 11:11:01 +11:00
aa7266385e
nouveau: always print nsource/nstatus regs on PGRAPH errors
2007-01-25 08:16:23 +11:00
7d4e6b1445
vblank interrupt fix
2007-01-24 16:33:21 +08:00
19ba074938
nouveau: fix getparam from 32-bit client on 64-bit kernel
2007-01-19 15:41:51 +11:00
4291df69bd
nouveau: re-add 6150 Go pciid (0x0244)
2007-01-19 15:16:18 +11:00
a40de938fa
nouveau: cleanup nv30_graph.c
2007-01-18 21:40:21 -05:00
ab72a7714e
nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching.
2007-01-18 21:40:21 -05:00
bd0418cb01
add missing quadro id
2007-01-18 17:35:28 +11:00
78a4f5c1bc
nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.
...
Hook into nv20 pgraph switching functions (they're identical for nv3x).
Actually call nv30_pgraph_context_init so the ctx_table is allocated.
Thanks to Carlos Martin for the help.
2007-01-17 08:46:59 -05:00
fdbc34fab0
nouveau: opps nv20 ctx ramin size was wrong
2007-01-14 20:04:20 +01:00
06cd155595
nouveau: opps restored the wrong channel
2007-01-13 23:30:43 +01:00
f04347f371
nouveau: nv20 graph ctx switch.
...
Untested...
2007-01-13 23:19:41 +01:00
cd5f543b2f
nouveau: first step to make graph ctx works
...
It is still not working, but now we could use some 3D commands
without needed to run nvidia blob before.
2007-01-13 21:44:50 +01:00
4ae64a1b58
nouveau: add and indent pgraph regs
2007-01-13 21:44:50 +01:00
1967aa82cf
nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value.
2007-01-13 12:32:50 +01:00
1bad7e0d02
nouveau : remove useless init : we clear RAMIN before
2007-01-12 20:31:18 +01:00
Matthieu Castet
Eric Anholt
Stephane Marchesin
Dave Airlie
Nian Wu
Ben Skeggs
Oliver McFadden
Patrice Mandin
Thomas Hellstrom
Nian Wu
Jakob Bornecrantz
B. Rathmann
Wang Zhenyu
Aapo Tahkola
Michel Dänzer
Ben Skeggs
Zou Nan hai
Jeremy Kolb
Dave Jones
Matthieu Castet