Commit Graph

56 Commits (24c09faec1c47260cd280221fa72fe18a12efef9)

Author SHA1 Message Date
Matthieu Castet 59784116bf nouveau : fix fifo context size for nv10 2007-05-08 21:20:25 +02:00
Ben Skeggs 674cefd4fe nouveau: move card initialisation into the drm
The PGRAPH init for the various cards will need cleaning up at some point,
a lot of the values written there are per-context state left over from the
all the hardcoding done in the ddx.

It's possible some cards get broken by this commit, let me know.
Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
2007-03-26 20:59:37 +10:00
Ben Skeggs 4988fa4886 nouveau: rework nouveau_fifo_alloc() so the drm can create internal FIFOs 2007-03-23 15:25:37 +11:00
Ben Skeggs 2bb9de96d5 nouveau: remove unused cruft 2007-03-23 13:45:29 +11:00
Ben Skeggs e22225416a nouveau: support multiple channels per client (breaks drm interface) 2007-03-21 17:57:47 +11:00
Ben Skeggs 90f8c691a5 nouveau: make sure cmdbuf object gets destroyed 2007-03-13 14:55:54 +11:00
Ben Skeggs 1775202cf9 nouveau: associate all created objects with a channel + cleanups 2007-03-13 14:55:54 +11:00
Patrice Mandin 0cd5c650d1 nouveau: PUT,GET, not 2xPUT 2007-03-11 14:02:40 +01:00
Ben Skeggs 72caa48c82 nouveau: intrusive drm interface changes
graphics objects:
	- No longer takes flags/dmaobj parameters, requires some major changes
	  to the ddx to setup the object through the FIFO.  This change is
	  likely to cause breakages on some cards (tested on NV05,NV28,NV35,
	  NV40 and NV4E).
dma objects:
	- now takes a "class" parameter, not really used yet but we may need
	  it at some point.
	- parameters are checked, so clients can't randomly create DMA objects
	  pointing at whatever they feel like.
misc:
	- Added FB_SIZE/AGP_SIZE getparams
	- Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR
	- Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't
	  NOTIFICATION_PENDING.
2007-02-28 15:41:53 +11:00
Stephane Marchesin f524870184 nouveau: fix the build on big endian (thanks CyberFoxx) 2007-02-14 00:08:55 +01:00
Stephane Marchesin 17985f07d6 nouveau: more work on the nv04 context switch code. 2007-02-06 01:17:32 +01:00
Stephane Marchesin 8c663b4e56 nouveau: and of course, I was missing the last nv04 piece. 2007-02-03 06:13:27 +01:00
Stephane Marchesin 5a072f32c8 nouveau: rename registers to their proper names. 2007-02-03 04:57:06 +01:00
Patrice Mandin 6d9ef1a960 nouveau: simplify and fix BIG_ENDIAN flags 2007-01-25 23:06:48 +01:00
Jeremy Kolb ab72a7714e nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching. 2007-01-18 21:40:21 -05:00
Jeremy Kolb 78a4f5c1bc nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.
Hook into nv20 pgraph switching functions (they're identical for nv3x).
Actually call nv30_pgraph_context_init so the ctx_table is allocated.

Thanks to Carlos Martin for the help.
2007-01-17 08:46:59 -05:00
Matthieu Castet f04347f371 nouveau: nv20 graph ctx switch.
Untested...
2007-01-13 23:19:41 +01:00
Matthieu Castet cd5f543b2f nouveau: first step to make graph ctx works
It is still not working, but now we could use some 3D commands
without needed to run nvidia blob before.
2007-01-13 21:44:50 +01:00
Matthieu Castet 1bad7e0d02 nouveau : remove useless init : we clear RAMIN before 2007-01-12 20:31:18 +01:00
Jeremy Kolb 4297a83b48 nouveau: get nv30 context switching to work.
* Pulled in some registers from nv10reg.h.  Needed for context switching.
* Filled in nv30 graphics context (based on nv40_graph.c).
* Figure out nv30 context table, set up on context creation.  Allows the cards automatic switching to work.
2007-01-12 00:14:54 -05:00
Ben Skeggs faa4612299 nouveau: avoid allocating vram that's used as instance memory. 2007-01-08 00:44:02 +11:00
Matthieu Castet 0f95ddc428 Merge branch 'master' of git+ssh://matc@git.freedesktop.org/git/mesa/drm/ 2007-01-05 19:41:12 +01:00
Matthieu Castet 9d167f1f4b Add basic pgraph context for nv10.
It only fake a context switch : pgraph state are not save/restored.
2007-01-05 19:40:11 +01:00
Stephane Marchesin f80659bc29 Cleanup the nv04 fifo code a bit. 2007-01-05 19:37:06 +01:00
Ben Skeggs 91855bb254 nouveau: oops, forgot to free RAMIN.. 2007-01-02 16:35:00 +11:00
Ben Skeggs 41da9fd2e5 nouveau: Hook up grctx code for NV4x.
This is enough to get grctx switching going on my NV40 and C51 after
the binary driver has initialised the card first.

Bumping the drm patchlevel because the ddx needs some modifications to
have NV4x work at all with these changes.
2007-01-02 15:08:04 +11:00
Ben Skeggs 2c3bc69ba2 nouveau: Only clobber PFIFO if no channels are already alloc'd
With this change the GPU is responsible for doing the channel switch
itself.  This is needed for the upcoming NV4x PGRAPH context work as
we don't yet know enough to manually swap PGRAPH contexts.
2007-01-02 14:41:34 +11:00
Ben Skeggs 9e019df757 nouveau: Alloc cmdbuf for each channel individually 2006-12-26 23:30:26 +11:00
Ben Skeggs b7586ab539 nouveau: save/restore endianness flag on FIFO switch
This makes my G5 survive glxinfo and nouveau_demo - airlied
2006-12-21 17:47:10 +11:00
Ben Skeggs 1a40f3318c Port remaining NV4 RAMIN access from the ddx into the drm.
Should fix lockups seen on NV4 cards.
2006-12-12 00:11:42 +11:00
Stephane Marchesin 30acb90a60 Merge the pciid work.
Add getparams for AGP and FB physical adresses.
Fix the MEM_ALLOC issue properly.
Fix context switches for nv44.
Change the DRM version to 0.0.1.
2006-12-03 10:02:54 +01:00
Ben Skeggs 80d75cf695 Use nouveau_mem.c to allocate RAMIN. 2006-11-30 10:31:42 +11:00
Ben Skeggs b1a9a76971 Wrap access to objects in RAMIN.
This will make it easier to support extra RAMIN in vram at a later point.
2006-11-30 08:35:42 +11:00
Matthieu Castet f48a7685bd For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context.
When cleaning a fifo, we shouldn't assume everybody use nv40 ;)
Fill DMA_SUBROUTINE fill correct value.
2006-11-28 21:32:03 +01:00
Ben Skeggs 9ac7a8b0b4 Only return FIFO number if the FIFO is marked as in use.. 2006-11-18 10:09:29 +11:00
Ben Skeggs e9194dd1b0 Check some return vals, fixes a couple of oopses. 2006-11-18 10:03:45 +11:00
Ben Skeggs 18bba3fa29 Dump some useful info when a PGRAPH error occurs.
The "channel" detect doesn't work on my nv40, but the rest
seems to produce sane info.
2006-11-17 08:05:23 +11:00
Ben Skeggs 2fd812f8ef Completely untested NV10/20/30 FIFO context switching changes. 2006-11-14 09:00:31 +11:00
Ben Skeggs 7002082944 Restructure initialisation a bit.
- Do important card init in firstopen
 - Give each channel it's own cmdbuf dma object
 - Move RAMHT config state to the same place as RAMRO/RAMFC
 - Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-14 08:11:49 +11:00
Ben Skeggs 9ef4bbc66c Hack around yet another "X restart borkage without nouveau.ko reload" problem.
On X init, PFIFO and PGRAPH are reset to defaults.  This causes the GPU to
loose the configuration done by the drm.  Perhaps a CARD_INIT ioctl a proper
solution to having this problem again in the future..
2006-11-14 04:51:13 +11:00
Dave Airlie 2dd3c039fd fixup fifo size so it is page aligned 2006-11-06 11:42:15 +11:00
Ben Skeggs b5cf0d635c Remove hack which delays activation of a additional channel. The previously active channel's state is saved to RAMFC before PFIFO gets clobbered. 2006-10-18 02:37:19 +11:00
Ben Skeggs 4b43ee63f9 NV40: *Now* fifo ctx switching works for me..
Ok, I lied before.. it was a fluke it worked and required magic to repeat it..
It actually helps to fill in RAMFC entries in the correct place.

The code also clears RAMIN entirely instead of just the hash-table.
2006-10-17 12:33:49 +11:00
Ben Skeggs 98e718d48f NV40: FIFO context switching now WorksForMe(tm) 2006-10-17 07:29:31 +11:00
Ben Skeggs 1943f39d8c Setup NV40 RAMFC (in wrong location.. but anyway), rearrange the RAMFC setup code a bit. 2006-10-17 06:37:40 +11:00
Stephane Marchesin 2c5b91aecf Again more work on context switches. They work, sometimes. And when they do they seem to screw up the PGRAPH state. 2006-10-14 16:36:11 +02:00
Stephane Marchesin 3a0cd7c7e2 Add the missing breaks. 2006-10-14 01:21:31 +02:00
Stephane Marchesin b509abe413 Fix the fifo context size on nv10, nv20 and nv30. 2006-10-13 22:35:22 +02:00
Ben Skeggs 4988074794 Fix some randomness in activating a second channel on NV40 (odd GET/PUT vals). Ch 1 GET now advances, but no ctx_switch. 2006-10-14 06:57:49 +11:00
Stephane Marchesin 7ef44b2b8d Still more work on the context switching code. 2006-10-12 17:31:49 +02:00