Commit Graph

6160 Commits (290d29d9794813a2fe0578dbb905ad09bc810516)

Author SHA1 Message Date
Damien Lespiau 1489811a80 intel/test_decode: Allow gen8 to be infered from the batch filenames
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-12-13 18:18:53 +00:00
Damien Lespiau bd73fd02e9 gitignore: Ignore various generated files
- *.log/*.trs are generated by make check
- TAGS are generated by make tags
- build-aux, config.h.in~ by autoconf
- *.sw? are temporary files create by vim
- name_from_fd wasn't ignored yet for some reason

v2: Ignore *~ as well (Daniel Vetter)

Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-12-13 18:17:25 +00:00
Marek Olšák 4c5de721c4 Bump the version to 2.4.50 2013-12-03 19:50:22 +01:00
Keith Packard c3d96897de intel: Track known prime buffers for re-use
If the application sends us a file descriptor pointing at a prime
buffer that we've already got, we have to re-use the same bo_gem
structure or chaos will result.

Track the set of all known prime objects and look to see if the kernel
has returned one of those for a new file descriptor.

Also checks for prime buffers in the flink case.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-26 21:45:40 -08:00
Michel Dänzer c8a437f4c7 radeon: Update unaligned offset for 2D->1D tiling transition on SI
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71983

Tested-by: Arek Ruśniak <arek.rusi@gmail.com>
2013-11-26 18:16:03 +09:00
Marek Olšák 7ddc98f92f Bump the version for release 2013-11-23 01:27:57 +01:00
Marek Olšák 3f46489022 radeon: handle P16 pipe configs for Hawaii 2013-11-23 00:35:42 +01:00
Michel Dänzer f0e399d8f0 radeon: don't overallocate stencil by 4 on SI and CIK
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2013-11-23 00:35:42 +01:00
Marek Olšák 67d92404d6 radeon: implement 2D tiling for CIK
Bug fixes and simplification by Marek.
We have to use the tile index of 0 for non-MSAA depth-stencil after all.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-23 00:35:39 +01:00
Michel Dänzer ce8af45425 radeon: fix mipmap level 0 and 1 alignment for SI and CIK
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-23 00:35:34 +01:00
Ian Romanick 0c3fd8708f intel: Use memset instead of VG_CLEAR
The ioctl expects that certain fields will be zeroed, so we should allow
the helper function to actually work in non-Valgrind builds.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reported-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-20 11:55:07 -08:00
Thomas Hellstrom c601444a90 libdrm/mode: Update the encoder and connector defines
Update the defines to match the kernel drm_mode.h

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-19 18:15:30 +01:00
Ian Romanick 71beb7b079 libdrm: bump to 2.4.48 2013-11-15 18:01:08 -08:00
Ian Romanick 5a41b02504 intel: Add support for GPU reset status query ioctl
I would have just used the drmIoctl interface directly in Mesa, but the
ioctl needs some data from the drm_intel_context that is not exposed
outside libdrm.

This ioctl is in the drm-intel-next tree as b635991.

v2: Update based on Mika's kernel work.

v3: Fix compile failures from last-minute typos.  Sigh.

v4: Import the actual changes from the kernel i915_drm.h.  Only comments
on some fields of drm_i915_reset_stats differed.  There are still some
deltas between the kernel i915_drm.h and the one in libdrm, but those
can be resolved in other patches.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v3]
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-15 11:31:49 -08:00
Alex Deucher 1a84eea45b radeon: add hawaii pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-13 11:33:31 -05:00
Alex Deucher efcc456030 radeon: add hawaii chip family
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-11-13 11:33:21 -05:00
Dave Airlie da738d1ed0 Revert "intel: Add support for GPU reset status query ioctl"
This reverts commit 6335e1d28c.

No taxation without representation, in other words no userspace without kernel
stuff being in a stable location, either drm-next but I'll accept drm-intel-next
for intel specific stuff.
2013-11-08 16:40:18 +10:00
Ian Romanick 6335e1d28c intel: Add support for GPU reset status query ioctl
I would have just used the drmIoctl interface directly in Mesa, but the
ioctl needs some data from the drm_intel_context that is not exposed
outside libdrm.

v2: Update based on Mika's kernel work.

v3: Fix compile failures from last-minute typos.  Sigh.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-07 19:14:31 -08:00
Damien Lespiau dad3c6b979 intel/bdw: Update MI_BATCH_BUFFER_START for aub dumps
The command now takes a 48bits address and is thus 1 dword longer.

v2 (Ben): commit message: s/byte/dword (Eric)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07 17:09:34 -08:00
Kenneth Graunke a0c126dced intel/bdw/aub: Update AUB trace block writes for 48-bit addressing.
Since our aub file dumping's GTT handling is totally fake, we always put
everything in the low 4GB anyway and shouldn't ever need to set
AddressHigh to anything other than 0.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
[ben: slight commit message change]
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07 17:09:18 -08:00
Damien Lespiau 946f847dc6 intel/bdw: Add gen8 to the decode init
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07 17:09:07 -08:00
Ben Widawsky 5b348f3ac0 intel/bdw: Handle gen8 bufmgr_init
[bwidawsk: Added Damien's SOB]
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07 17:07:32 -08:00
Ben Widawsky 6ea20a0fe2 intel/bdw: Add broadwell chipset IDs
v2: Rename s/<SECRET>/IRIS/

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-07 17:07:25 -08:00
Maarten Lankhorst 482abbfafb nouveau: prevent undefined behavior in nouveau_pushbuf_reloc with gcc-4.8
Reported-by: ronald645@gmail.com
Bisected-by (gcc): Andreas Radke <a.radke@arcor.de>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71116
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
2013-11-07 13:37:49 +01:00
Keith Packard ebff7a1e22 Add DRM_MODE_PAGE_FLIP_ASYNC define
This exposes the kernel API for performing asynchronous flips

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-11-06 19:49:39 -08:00
Kenneth Graunke 45810d3d75 intel: Add MI_LOAD_REGISTER_MEM to intel_decode.c.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-10-29 20:57:21 -07:00
Kenneth Graunke 551aac4375 intel: Add the Gen6+ version of MI_REPORT_PERF_COUNT to intel_decode.c.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-10-29 20:57:02 -07:00
Ben Widawsky 951ebe0081 libdrm: bump to 2.4.47 2013-10-11 09:47:45 -07:00
Kristian Høgsberg 9c52c3dc47 intel: Set bo size from lseek if kernel supports it
The various create and open functions set the buffer size, but
drm_intel_bo_gem_create_from_prime() is an exception.  In the 3.12 kernel
we can now use lseek on the prime fd to determine the size of the bo.
Use that and override the userprovided size.  If the kernel doesn't
support this, we get an error and fall back to the user provided size.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2013-10-10 14:41:40 -07:00
Damien Lespiau ddbbdb13d8 drm: Introduce a drmSetClientCap() wrapper
That wraps around the new DRM_SET_CLIENT_CAP ioctl.

v2: SET_CAP -> SET_CLIENT_CAP renaming

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-09-30 13:35:49 +01:00
Damien Lespiau 2dd7054781 drm: Sync the DRM_SET_CLIENT_CAP ioctl definition
v2: SET_CAP -> SET_CLIENT_CAP renaming

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-09-30 13:35:49 +01:00
Damien Lespiau edf5c7cde5 drm: Synchronize the stereo 3D mode flags from the kernel headers
v2: stereo layouts are now an enum (Daniel Vetter)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-09-30 13:35:49 +01:00
Marek Olšák 75f747b919 radeon: fix pitch alignment for non-power-of-two mipmaps on SI
This fixes VM protection faults.

I have a new piglit test which can iterate over all possible widths, heights,
and depths (including NPOT) and tests mipmapping with various texture targets.

After this is committed, I'll make a new release of libdrm and bump
the libdrm version requirement in Mesa.
2013-09-29 14:44:23 +02:00
Emil Velikov bf4a7cd4b2 configure: add AC_LANG_SOURCE call within AC_COMPILE_IFELSE
Documentation states that AC_*_IFELSE has to use AC_LANG_SOURCE or
friends in order to generate the source code to compile.
AC_LINK_IFELSE already handles this, thus convert AC_COMPILE_IFELSE
to silence the final autoconf warnings.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2013-09-24 08:52:47 -07:00
Daniel Kurtz 0f4452bb51 libdrm: Make some drm headers compatible with gcc -std=c89 -pedantic
The following minor changes were needed to these headers:
 * Convert // comments to /* */
 * No , after final member of enum

With these changes, these header files can be included by a program that
is built with gcc options:
  -std=c89 -Werror -pedantic

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-09-22 13:30:46 -07:00
Michel Dänzer a48d6e5621 radeon: Fix tiling mode index for 1D tiled depth/stencil surfaces on CIK
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-18 18:28:51 +02:00
Rob Clark b6da447c04 freedreno: add missing NOSYNC flag
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-09-11 15:55:59 -04:00
Ilia Mirkin d8954154fe modetest: allow setting a scaling factor when showing plane
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2013-09-11 11:25:32 -04:00
Ilia Mirkin b50826dbd6 modetest: add a -D option to specify a device to be used
This is helpful for differentiating between multiple devices that use
the same module.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2013-09-11 11:25:17 -04:00
Alex Deucher 58d0088831 radeon: pad CS to 8 DW
Aligns the IB to 8 DWs.  The aligns the IB to the
CP fetch size.  r6xx also require at least 4 DW
alignment to avoid a hw bug.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-06 15:58:56 -04:00
Alex Deucher 8a2e0fa917 radeon: add berlin pci ids
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-09-06 15:39:37 -04:00
Emil Velikov d18cd0c7cc intel: Update package name and description in libdrm_intel.pc
Currently the package name and description duplicate that of the
core libdrm. Update those to reflect reality.

Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
2013-08-30 12:10:50 -04:00
Emil Velikov db6a1b07d0 freedreno: set automake options to include subdir-objects
Handles automake complains about lack of forward-compatibility, due to the
source files in the kgsl and msm backends/folders.

Cc: Rob Clark <robclark@freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2013-08-30 11:37:14 -04:00
Emil Velikov 126c45828a freedreno: use local drm.h over the system one
Otherwise build will fail, as drm/drm.h is not available.

Cc: Rob Clark <robclark@freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2013-08-30 11:37:14 -04:00
Emil Velikov 4a8da02e52 tests/modetest: silence compiler warning about uninitialised variables
The compiler is unaware of that we have at least one crts/connector/plane
thus it complains that some of our variables will be used uninitialised.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2013-08-30 11:37:05 -04:00
Emil Velikov 0100473de6 tests/*version: add missing string.h header
Prodives memset() and strlen(), used in tests/setversion
tests/getversion respectively.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2013-08-30 11:36:20 -04:00
Rob Clark dba6bec3ab tests: add msm
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-08-30 11:36:20 -04:00
Rob Clark f17d417e28 freedreno: add support for msm drm
This adds support for the "msm" backend, using the upstream msm drm/kms
driver.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-08-28 15:51:04 -04:00
Rob Clark b2b1885dfc freedreno: support either kgsl or msm
Split out common code and backend.  Current backend is for 'kgsl'
android driver, but a new backend will provide support for the
upstream msm drm/kms driver.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2013-08-28 15:50:15 -04:00
Laurent Pinchart 3c967e7155 modetest: Allocate NV buffers large enough for the two planes
Multiple the image height by 1.5 for NV12/NV21 and by 2 for NV16/NV61 to
make room for the chroma plane.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2013-08-05 14:21:45 +02:00