1e4c7d69f5
Some cleanup. A buffer object should only have one active memory type.
2007-01-29 13:37:02 +01:00
ee4ac5c897
nouveau: determine chipset type at startup, instead of every time we use it.
2007-01-28 23:48:33 +11:00
c744bfde2d
make works ctx switch on nv10.
2007-01-26 21:57:44 +01:00
9c03ca81e7
nouveau: oops, wrong indexing in nv17 regs
2007-01-26 21:05:59 +01:00
5534c90ff3
nouveau: read gpu type once
2007-01-26 19:54:35 +01:00
05d3ed472e
nouveau: only save/restore nv17 regs on nv17,18 hw
2007-01-26 19:25:49 +01:00
e7ba15a003
nouveau: add extra pgraph registers
2007-01-26 19:24:34 +01:00
d4c9f135b5
nouveau: add some nv10 pgraph defines
2007-01-26 18:10:31 +01:00
6d9ef1a960
nouveau: simplify and fix BIG_ENDIAN flags
2007-01-25 23:06:48 +01:00
3886b7e629
Merge branch 'master' into crestline
2007-01-25 13:30:46 -08:00
582637641a
Remove a scary error printed when we were leaking memory caches.
...
We don't use memory caches anymore...
Fix memory accounting initialization to only use low or DMA32 memory.
2007-01-25 14:27:29 +01:00
90ae39d2f0
nouveau: nv4c default context
2007-01-25 11:11:01 +11:00
aa7266385e
nouveau: always print nsource/nstatus regs on PGRAPH errors
2007-01-25 08:16:23 +11:00
7d4e6b1445
vblank interrupt fix
2007-01-24 16:33:21 +08:00
19ba074938
nouveau: fix getparam from 32-bit client on 64-bit kernel
2007-01-19 15:41:51 +11:00
4291df69bd
nouveau: re-add 6150 Go pciid (0x0244)
2007-01-19 15:16:18 +11:00
a40de938fa
nouveau: cleanup nv30_graph.c
2007-01-18 21:40:21 -05:00
ab72a7714e
nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching.
2007-01-18 21:40:21 -05:00
bd0418cb01
add missing quadro id
2007-01-18 17:35:28 +11:00
78a4f5c1bc
nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.
...
Hook into nv20 pgraph switching functions (they're identical for nv3x).
Actually call nv30_pgraph_context_init so the ctx_table is allocated.
Thanks to Carlos Martin for the help.
2007-01-17 08:46:59 -05:00
9f5cda44db
Merge branch 'master' into crestline
2007-01-16 09:49:20 +08:00
fdbc34fab0
nouveau: opps nv20 ctx ramin size was wrong
2007-01-14 20:04:20 +01:00
06cd155595
nouveau: opps restored the wrong channel
2007-01-13 23:30:43 +01:00
f04347f371
nouveau: nv20 graph ctx switch.
...
Untested...
2007-01-13 23:19:41 +01:00
cd5f543b2f
nouveau: first step to make graph ctx works
...
It is still not working, but now we could use some 3D commands
without needed to run nvidia blob before.
2007-01-13 21:44:50 +01:00
4ae64a1b58
nouveau: add and indent pgraph regs
2007-01-13 21:44:50 +01:00
1967aa82cf
nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value.
2007-01-13 12:32:50 +01:00
69a98d89d5
nouveau: add missing symlink
2007-01-13 08:43:15 +11:00
1bad7e0d02
nouveau : remove useless init : we clear RAMIN before
2007-01-12 20:31:18 +01:00
9d3deddc4a
Delay for a usec while spinning waiting for ring buffer space.
...
This means the loop will wait up to ~10ms for ring buffer space to become
available, rather than just however long it takes to check the space 10000
times. This matches other drivers' behavior when waiting for ring buffer/fifo
space.
2007-01-12 11:24:50 -08:00
4297a83b48
nouveau: get nv30 context switching to work.
...
* Pulled in some registers from nv10reg.h. Needed for context switching.
* Filled in nv30 graphics context (based on nv40_graph.c).
* Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-12 00:14:54 -05:00
8ff026723c
radeon: Fix u32 overflows when determining AGP base address in card space.
...
The overflows could lead to the AGP aperture overlapping the framebuffer area
in the card's address space when the latter is located at the very end of the
32 bit address space, which would result in a freeze on X server startup,
probably because the card read commands from the framebuffer instead of from
AGP.
See http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=392915 .
2007-01-11 09:02:07 +01:00
125f3ff367
Revert "nouveau: Fill in context_init for nv10-nv3x."
...
This reverts ac076cb9af
2007-01-10 15:19:47 +11:00
ac076cb9af
nouveau: Fill in context_init for nv10-nv3x.
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Fill in the context with the values from PFIFO_CACH1. This should work from nv10 through the nv30 series.
2007-01-09 23:12:37 -05:00
ec12209c76
nouveau: Don't use DRIVER_USE_MTRR, we already setup our own mtrr over vram.
2007-01-10 04:42:09 +01:00
f6ba3b2603
ttm: make ttm alloc/free into alloc_pages/free_pages
...
Add a vmalloc flag to the page flags
2007-01-09 15:51:29 +11:00
a70aedd5fc
novueau: try resource 3 if resource 2 is 0 length
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This happens on my NV43 PPC
2007-01-09 13:48:38 +11:00
deba42ef32
nouveau: fix nv4a context size.
2007-01-08 20:55:57 +01:00
22821cf01d
add export symbol for memory manager
2007-01-08 22:27:27 +11:00
6ac742d95d
Align whitespace with master
2007-01-07 23:05:39 -08:00
c5aaf7648d
Merge branch 'master' into crestline
...
Conflicts:
shared-core/i915_drm.h
Whitespace change only
2007-01-07 22:37:40 -08:00
d0080d71b9
nouveau: nv4a context support.
2007-01-08 05:02:40 +01:00
6eaa1272b4
Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm
2007-01-08 03:50:34 +01:00
5bf60c9d6c
i830: complete fix for i830 maps
2007-01-08 13:09:51 +11:00
26bf6d9b5b
nouveau: oops
2007-01-08 12:50:44 +11:00
128d87a3dd
nouveau: nv43 context stuff
2007-01-08 12:47:51 +11:00
b147c39263
drm: remove drm_follow_page, and drm_ioremap and ioremapfree
...
This comes from the Re: [patch] paravirt: isolate module ops on lkml
It needs some testing, please report any regressions caused.
Signed-off-by: Dave Airlie <airlied@linux.ie>
2007-01-08 11:47:15 +11:00
fe5770b89e
fixup i810/i830 to use drm_core_ioremap instead of drm_ioremap
2007-01-08 11:46:54 +11:00
1f0f7d7a18
nouveau: fix a stupid bug from me.
2007-01-08 00:11:39 +01:00
faa4612299
nouveau: avoid allocating vram that's used as instance memory.
2007-01-08 00:44:02 +11:00
Thomas Hellstrom
Ben Skeggs
Matthieu Castet
Patrice Mandin
Nian Wu
Zou Nan hai
Jeremy Kolb
Dave Jones
Xiang, Haihao
Matthieu Castet
Stephane Marchesin
Dave Airlie
Michel Dänzer
Keith Packard
Christoph Hellwig
Dave Airlie