Stephane Marchesin
e64dbef911
nouveau: add NV04 registers required for PGRAPH context switching.
2007-02-03 04:23:09 +01:00
Matthieu Castet
55f7859a25
nouveau: nv ctx switch opps the size of array was wrong
2007-02-02 23:01:03 +01:00
Matthieu Castet
63cf3b3da7
nouveau: nv10 ctx switch, some regs are nv17+ only
2007-02-02 20:08:33 +01:00
Thomas Hellstrom
6c04185857
via: Try to improve command-buffer chaining.
...
Bump driver date and patchlevel.
2007-02-02 09:22:30 +01:00
Thomas Hellstrom
70bba11bc7
Disable AGP DMA for chips with the new 3D engine.
2007-02-02 09:22:15 +01:00
Thomas Hellstrom
3024f23c65
memory manager: Make device driver aware of different memory types.
...
Memory types are either fixed (on-card or pre-bound AGP) or not fixed
(dynamically bound) to an aperture. They also carry information about:
1) Whether they can be mapped cached.
2) Whether they are at all mappable.
3) Whether they need an ioremap to be accessible from kernel space.
In this way VRAM memory and, for example, pre-bound AGP appear
identical to the memory manager.
This also makes support for unmappable VRAM simple to implement.
2007-01-31 14:50:57 +01:00
Ben Skeggs
ee4ac5c897
nouveau: determine chipset type at startup, instead of every time we use it.
2007-01-28 23:48:33 +11:00
Matthieu Castet
c744bfde2d
make works ctx switch on nv10.
2007-01-26 21:57:44 +01:00
Patrice Mandin
9c03ca81e7
nouveau: oops, wrong indexing in nv17 regs
2007-01-26 21:05:59 +01:00
Patrice Mandin
5534c90ff3
nouveau: read gpu type once
2007-01-26 19:54:35 +01:00
Patrice Mandin
05d3ed472e
nouveau: only save/restore nv17 regs on nv17,18 hw
2007-01-26 19:25:49 +01:00
Patrice Mandin
e7ba15a003
nouveau: add extra pgraph registers
2007-01-26 19:24:34 +01:00
Patrice Mandin
d4c9f135b5
nouveau: add some nv10 pgraph defines
2007-01-26 18:10:31 +01:00
Patrice Mandin
6d9ef1a960
nouveau: simplify and fix BIG_ENDIAN flags
2007-01-25 23:06:48 +01:00
Ben Skeggs
90ae39d2f0
nouveau: nv4c default context
2007-01-25 11:11:01 +11:00
Ben Skeggs
aa7266385e
nouveau: always print nsource/nstatus regs on PGRAPH errors
2007-01-25 08:16:23 +11:00
Zou Nan hai
7d4e6b1445
vblank interrupt fix
2007-01-24 16:33:21 +08:00
Ben Skeggs
19ba074938
nouveau: fix getparam from 32-bit client on 64-bit kernel
2007-01-19 15:41:51 +11:00
Ben Skeggs
4291df69bd
nouveau: re-add 6150 Go pciid (0x0244)
2007-01-19 15:16:18 +11:00
Jeremy Kolb
a40de938fa
nouveau: cleanup nv30_graph.c
2007-01-18 21:40:21 -05:00
Jeremy Kolb
ab72a7714e
nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching.
2007-01-18 21:40:21 -05:00
Dave Jones
bd0418cb01
add missing quadro id
2007-01-18 17:35:28 +11:00
Jeremy Kolb
78a4f5c1bc
nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.
...
Hook into nv20 pgraph switching functions (they're identical for nv3x).
Actually call nv30_pgraph_context_init so the ctx_table is allocated.
Thanks to Carlos Martin for the help.
2007-01-17 08:46:59 -05:00
Matthieu Castet
fdbc34fab0
nouveau: opps nv20 ctx ramin size was wrong
2007-01-14 20:04:20 +01:00
Matthieu Castet
06cd155595
nouveau: opps restored the wrong channel
2007-01-13 23:30:43 +01:00
Matthieu Castet
f04347f371
nouveau: nv20 graph ctx switch.
...
Untested...
2007-01-13 23:19:41 +01:00
Matthieu Castet
cd5f543b2f
nouveau: first step to make graph ctx works
...
It is still not working, but now we could use some 3D commands
without needed to run nvidia blob before.
2007-01-13 21:44:50 +01:00
Matthieu Castet
4ae64a1b58
nouveau: add and indent pgraph regs
2007-01-13 21:44:50 +01:00
Stephane Marchesin
1967aa82cf
nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value.
2007-01-13 12:32:50 +01:00
Matthieu Castet
1bad7e0d02
nouveau : remove useless init : we clear RAMIN before
2007-01-12 20:31:18 +01:00
Haihao Xiang
9d3deddc4a
Delay for a usec while spinning waiting for ring buffer space.
...
This means the loop will wait up to ~10ms for ring buffer space to become
available, rather than just however long it takes to check the space 10000
times. This matches other drivers' behavior when waiting for ring buffer/fifo
space.
2007-01-12 11:24:50 -08:00
Jeremy Kolb
4297a83b48
nouveau: get nv30 context switching to work.
...
* Pulled in some registers from nv10reg.h. Needed for context switching.
* Filled in nv30 graphics context (based on nv40_graph.c).
* Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-12 00:14:54 -05:00
Michel Dänzer
8ff026723c
radeon: Fix u32 overflows when determining AGP base address in card space.
...
The overflows could lead to the AGP aperture overlapping the framebuffer area
in the card's address space when the latter is located at the very end of the
32 bit address space, which would result in a freeze on X server startup,
probably because the card read commands from the framebuffer instead of from
AGP.
See http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=392915 .
2007-01-11 09:02:07 +01:00
Dave Airlie
a70aedd5fc
novueau: try resource 3 if resource 2 is 0 length
...
This happens on my NV43 PPC
2007-01-09 13:48:38 +11:00
Stephane Marchesin
deba42ef32
nouveau: fix nv4a context size.
2007-01-08 20:55:57 +01:00
Stephane Marchesin
d0080d71b9
nouveau: nv4a context support.
2007-01-08 05:02:40 +01:00
Stephane Marchesin
6eaa1272b4
Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm
2007-01-08 03:50:34 +01:00
Ben Skeggs
26bf6d9b5b
nouveau: oops
2007-01-08 12:50:44 +11:00
Ben Skeggs
128d87a3dd
nouveau: nv43 context stuff
2007-01-08 12:47:51 +11:00
Stephane Marchesin
1f0f7d7a18
nouveau: fix a stupid bug from me.
2007-01-08 00:11:39 +01:00
Ben Skeggs
faa4612299
nouveau: avoid allocating vram that's used as instance memory.
2007-01-08 00:44:02 +11:00
Ben Skeggs
cd3711455e
nouveau: map pci resource 2 on >=nv40
2007-01-08 00:44:02 +11:00
Keith Packard
31daf66962
Revert i915 drm driver name to i915; miniglx doesn't work otherwise
...
Yes, this driver supports the new memory manager, that is indicated by the
version number being >= 1.7.
2007-01-06 17:40:50 -08:00
Wang Zhenyu
2851c9f5c6
Bump i915 minor for ARB_OC ioctl
2007-01-06 16:26:54 -08:00
Zou Nan hai
f7180349fd
i915: ARB_Occlusion_query(MMIO ioctl) support.
...
This adds a new ioctl for passing counter information from the chip back to
applications, these counters include the data needed to perform OC.
2007-01-06 16:22:08 -08:00
Ben Skeggs
1f1714cf3d
nouveau: get c51 doing glxgears without the binary driver's help.
2007-01-06 18:05:21 +11:00
Ben Skeggs
dbb0d979cc
nouveau: Use PMC_BOOT_0 to determine which ctx_voodoo to load.
2007-01-06 17:50:00 +11:00
Stephane Marchesin
528ab8ce40
nouveau: oops, we don't need OS_HAS_MTRR actually.
2007-01-05 20:59:45 +01:00
Stephane Marchesin
d99c7c27e2
Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm
2007-01-05 20:50:46 +01:00
Stephane Marchesin
025f281bbf
nouveau: Add an mtrr over the whole FB
2007-01-05 20:49:34 +01:00
Matthieu Castet
0f95ddc428
Merge branch 'master' of git+ssh://matc@git.freedesktop.org/git/mesa/drm/
2007-01-05 19:41:12 +01:00
Matthieu Castet
9d167f1f4b
Add basic pgraph context for nv10.
...
It only fake a context switch : pgraph state are not save/restored.
2007-01-05 19:40:11 +01:00
Stephane Marchesin
f80659bc29
Cleanup the nv04 fifo code a bit.
2007-01-05 19:37:06 +01:00
Michel Dänzer
4fe2858f53
i915: Fix a DRM_ERROR that should be DRM_DEBUG.
...
It would clutter up the kernel output in a situation which is legitimate before
X.org 7.2 and handled correctly by the 3D driver.
2007-01-02 10:05:48 +01:00
Ben Skeggs
91855bb254
nouveau: oops, forgot to free RAMIN..
2007-01-02 16:35:00 +11:00
Ben Skeggs
861017e6d5
nouveau: Hookup nv40_graph_init.
...
Now I can get 3D + working grctx switching on my NV40 without
the binary driver initialising the card first. However, this
change also breaks 3D on my C51 even *with* the binary driver's
help. So, it's likely that the weird voodoo is card-specific.
2007-01-02 15:56:10 +11:00
Ben Skeggs
41da9fd2e5
nouveau: Hook up grctx code for NV4x.
...
This is enough to get grctx switching going on my NV40 and C51 after
the binary driver has initialised the card first.
Bumping the drm patchlevel because the ddx needs some modifications to
have NV4x work at all with these changes.
2007-01-02 15:08:04 +11:00
Ben Skeggs
0e0d954584
nouveau: Add nv40-specific PGRAPH code, not hooked up yet.
2007-01-02 14:52:43 +11:00
Ben Skeggs
2c3bc69ba2
nouveau: Only clobber PFIFO if no channels are already alloc'd
...
With this change the GPU is responsible for doing the channel switch
itself. This is needed for the upcoming NV4x PGRAPH context work as
we don't yet know enough to manually swap PGRAPH contexts.
2007-01-02 14:41:34 +11:00
Thomas Hellstrom
a16a8a47cd
Add some new via chipsets.
...
Disable 3D functionality and AGP DMA for chipsets with the DX9 3D engine.
2006-12-28 22:17:08 +01:00
Thomas Hellstrom
7859bd61d3
Leftover from previous commit.
2006-12-27 19:46:46 +01:00
Thomas Hellstrom
2980ec22a1
Allow for non-power-of-two texture pitch alignment.
2006-12-27 19:38:33 +01:00
Ben Skeggs
c38ede0667
nouveau: return the *actual* type of memory alloc'd to userspace
2006-12-27 01:58:57 +11:00
Ben Skeggs
9e019df757
nouveau: Alloc cmdbuf for each channel individually
2006-12-26 23:30:26 +11:00
Ben Skeggs
b7586ab539
nouveau: save/restore endianness flag on FIFO switch
...
This makes my G5 survive glxinfo and nouveau_demo - airlied
2006-12-21 17:47:10 +11:00
Thomas Hellstrom
3b47b27558
Some via PCI posting flushes.
2006-12-20 13:04:21 +01:00
Dave Airlie
e5c4a26a29
Merge branch 'nouveau-1'
2006-12-20 10:30:16 +11:00
Dave Airlie
7458909bea
fixup i915 return values from kernel
2006-12-19 21:48:18 +11:00
Dave Airlie
07635f26a9
fix comment in r128
2006-12-19 17:58:20 +11:00
Dave Airlie
c52dea9a7d
fix some sizes in sis_drv.h
2006-12-19 17:58:16 +11:00
Dave Airlie
8cc82c5033
remove inline from large function
2006-12-19 17:58:12 +11:00
Dave Airlie
13659357ad
make a savage function static from kernel
2006-12-19 17:58:09 +11:00
Dave Airlie
cb280ad3c0
fix missing DRM_ERR from kernel
2006-12-19 17:58:03 +11:00
Michel Dänzer
aefc7a3443
Unify radeon offset checking.
...
Replace r300_check_offset() with generic radeon_check_offset(), which doesn't
reject valid offsets when the framebuffer area is at the very end of the card's
32 bit address space. Make radeon_check_and_fixup_offset() use
radeon_check_offset() as well.
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=7697 .
2006-12-14 19:31:56 +01:00
Ben Skeggs
1a40f3318c
Port remaining NV4 RAMIN access from the ddx into the drm.
...
Should fix lockups seen on NV4 cards.
2006-12-12 00:11:42 +11:00
Stephane Marchesin
30acb90a60
Merge the pciid work.
...
Add getparams for AGP and FB physical adresses.
Fix the MEM_ALLOC issue properly.
Fix context switches for nv44.
Change the DRM version to 0.0.1.
2006-12-03 10:02:54 +01:00
Michel Dänzer
a97bb85c2a
Unshare drm_drawable.c again for now.
...
The current version didn't build on BSD, where the new functionality isn't used
yet anyway. Whoever changes that will hopefully be able to make the OSes share
this file as well.
2006-12-01 10:46:21 +01:00
Ben Skeggs
80d75cf695
Use nouveau_mem.c to allocate RAMIN.
2006-11-30 10:31:42 +11:00
Ben Skeggs
b1a9a76971
Wrap access to objects in RAMIN.
...
This will make it easier to support extra RAMIN in vram at a later point.
2006-11-30 08:35:42 +11:00
Matthieu Castet
f48a7685bd
For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context.
...
When cleaning a fifo, we shouldn't assume everybody use nv40 ;)
Fill DMA_SUBROUTINE fill correct value.
2006-11-28 21:32:03 +01:00
Michel Dänzer
ddcb994c3e
i915_vblank_tasklet: Try harder to avoid tearing.
...
Previously, if there were several buffer swaps scheduled for the same vertical
blank, all but the first blit emitted stood a chance of exhibiting tearing. In
order to avoid this, split the blits along slices of each output top to bottom.
2006-11-27 11:32:33 +01:00
Stephane Marchesin
0a364be289
Merge branch 'nouveau-1' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm into nouveau-1
2006-11-21 23:32:58 +01:00
Ben Skeggs
adf71cb29b
Don't spam dmesg if PMC_INTSTAT is 0
2006-11-21 11:41:46 +11:00
Ben Skeggs
9ac7a8b0b4
Only return FIFO number if the FIFO is marked as in use..
2006-11-18 10:09:29 +11:00
Ben Skeggs
e9194dd1b0
Check some return vals, fixes a couple of oopses.
2006-11-18 10:03:45 +11:00
Ben Skeggs
18bba3fa29
Dump some useful info when a PGRAPH error occurs.
...
The "channel" detect doesn't work on my nv40, but the rest
seems to produce sane info.
2006-11-17 08:05:23 +11:00
Stephane Marchesin
5e7f58474d
Merge branch 'nouveau-1' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm into nouveau-1
2006-11-16 14:47:52 +01:00
Ben Skeggs
2fd812f8ef
Completely untested NV10/20/30 FIFO context switching changes.
2006-11-14 09:00:31 +11:00
Ben Skeggs
7002082944
Restructure initialisation a bit.
...
- Do important card init in firstopen
- Give each channel it's own cmdbuf dma object
- Move RAMHT config state to the same place as RAMRO/RAMFC
- Make sure instance mem for objects is *after* RAM{FC,HT,RO}
2006-11-14 08:11:49 +11:00
Ben Skeggs
35bf8fb5cf
Merge branch 'nouveau-1' of git+ssh://git.freedesktop.org/git/mesa/drm into nouveau-1
2006-11-14 04:52:08 +11:00
Ben Skeggs
9ef4bbc66c
Hack around yet another "X restart borkage without nouveau.ko reload" problem.
...
On X init, PFIFO and PGRAPH are reset to defaults. This causes the GPU to
loose the configuration done by the drm. Perhaps a CARD_INIT ioctl a proper
solution to having this problem again in the future..
2006-11-14 04:51:13 +11:00
Stephane Marchesin
5a0cdf7db3
Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm into nouveau-1
2006-11-11 01:57:05 +01:00
Stephane Marchesin
1123ab0890
Fix memory detection on TNT2 M64/TNT2 vanta.
2006-11-10 02:18:38 +01:00
Eric Anholt
584acab6d6
Add drm_u64_t typedef on non-linux to fix libdrm build.
2006-11-07 09:36:40 -08:00
Dave Airlie
f7affda35b
drm: fixup page alignment on SAREA map on ppc64
2006-11-06 11:44:36 +11:00
Dave Airlie
2dd3c039fd
fixup fifo size so it is page aligned
2006-11-06 11:42:15 +11:00
Dave Airlie
5e55594061
use a uint64_t for this not a pointer
2006-11-06 11:41:51 +11:00
Dave Airlie
1e90b7ee8c
Merge branch 'master' into nouveau-1
...
Conflicts:
linux-core/Makefile.kernel
2006-11-06 08:03:18 +11:00
Ben Skeggs
0c34d0f31a
Leave the bottom 64kb of RAMIN untouched.
...
The binary driver will screw up either it's init or shutdown, leaving the
screen(s) in an unusable state without this. Something important in there?
2006-11-06 05:46:03 +11:00
Dave Airlie
94ab96c4d8
nouveau: add compat ioc32 support
2006-11-05 20:39:13 +11:00