d734992e6a
i915: Only wait for pending flips before asynchronous flips again.
2007-03-10 00:10:49 +01:00
0741064df4
i915: Do not wait for pending flips on both pipes at the same time.
...
The MI_WAIT_FOR_EVENT instruction does not support waiting for several events
at once, so this should fix the lockups with page flipping when both pipes are
enabled.
2007-03-09 16:39:13 +01:00
1b3a6d4775
nouveau: remove a hack that's not needed since the last interface change.
2007-03-07 21:17:45 +11:00
5bd0e52dba
nouveau: ack PFIFO interrupts at PFIFO, not PMC.
2007-03-07 21:00:55 +11:00
a33859184a
i915: Eliminate dev_priv->current_page.
...
Always use dev_priv->sarea_priv->pf_current_page directly. This allows clients
to modify it as well while they hold the HW lock, e.g. in order to sync pages
between pipes.
2007-02-28 17:48:56 +01:00
074e10b384
i915: Only clean up page flipping when the last client goes away, not any one.
2007-02-28 15:57:08 +01:00
1cdc1b6fba
i915: Don't emit waits for pending flips before emitting synchronous flips.
...
The assumption is that synchronous flips are not isolated usually, and waiting
for all of them could result in stalling the pipeline for long periods of time.
Also use i915_emit_mi_flush() instead of an old-fashioned way to achieve the
same effect.
2007-02-28 15:23:19 +01:00
fd0fed3f1e
i915: Fix test for synchronous flip affecting both pipes.
2007-02-28 12:33:56 +01:00
1a0d890a42
i915: Add support for scheduled buffer swaps to be done as flips.
...
Unfortunately, emitting asynchronous flips during vertical blank results in
tearing. So we have to wait for the previous vertical blank and emit a
synchronous flip.
2007-02-22 17:21:18 +01:00
5a40c043cc
Add DRM_VBLANK_FLIP.
...
Used to request that a scheduled buffer swap be done as a flip instead of a
blit.
2007-02-22 17:19:30 +01:00
6f89584e13
i915: Improved page flipping support, including triple buffering.
...
Pages are tracked independently on each pipe.
Bump the minor version for 3D clients to know page flipping is usable, and
bump driver date.
2007-02-19 15:08:40 +01:00
34aa3393d0
i915: Page flipping enhancements.
...
Leave it to the client to wait for the flip to complete when necessary,
but wait for a previous flip to complete before emitting another one. This
should help avoid unnecessary stalling of the ring due to pending flips.
Call i915_do_cleanup_pageflip() unconditionally in preclose.
2007-02-19 15:08:40 +01:00
078e430726
i915: Unify breadcrumb emission.
2007-02-19 15:08:40 +01:00
53aee3122a
I915 accelerated blit copy functional.
...
Fixed - to System memory copies are implemented by
flipping in a cache-coherent TTM,
blitting to it, and then flipping it out.
2007-02-09 16:36:53 +01:00
898aca1a66
Warning fix: correct type of i915_mmio argument.
2007-02-07 21:26:02 -08:00
ef9a9d3cd1
Define __iomem for systems without it.
2007-02-07 21:26:01 -08:00
8918748058
Add chip family flags to i915 driver, and fix a missing '"' in mach64 ID list.
2007-02-07 21:26:01 -08:00
c1fbd8a566
Checkpoint commit.
...
Flag handling and memory type selection cleanup.
glxgears won't start.
2007-02-07 17:25:13 +01:00
609e3b0375
Implement a policy for selecting memory types.
2007-02-06 14:20:33 +01:00
17985f07d6
nouveau: more work on the nv04 context switch code.
2007-02-06 01:17:32 +01:00
8c663b4e56
nouveau: and of course, I was missing the last nv04 piece.
2007-02-03 06:13:27 +01:00
0c13657c33
nouveau: plugin the nv04 graph init function.
2007-02-03 06:00:29 +01:00
7ab9e7f36f
nouveau: cleanup the nv04 pgraph save/restore mechanism.
2007-02-03 05:56:42 +01:00
d69902db3b
nouveau: fix nv04 graph routines for new register names.
2007-02-03 05:25:36 +01:00
5a072f32c8
nouveau: rename registers to their proper names.
2007-02-03 04:57:06 +01:00
e64dbef911
nouveau: add NV04 registers required for PGRAPH context switching.
2007-02-03 04:23:09 +01:00
55f7859a25
nouveau: nv ctx switch opps the size of array was wrong
2007-02-02 23:01:03 +01:00
63cf3b3da7
nouveau: nv10 ctx switch, some regs are nv17+ only
2007-02-02 20:08:33 +01:00
6c04185857
via: Try to improve command-buffer chaining.
...
Bump driver date and patchlevel.
2007-02-02 09:22:30 +01:00
70bba11bc7
Disable AGP DMA for chips with the new 3D engine.
2007-02-02 09:22:15 +01:00
3024f23c65
memory manager: Make device driver aware of different memory types.
...
Memory types are either fixed (on-card or pre-bound AGP) or not fixed
(dynamically bound) to an aperture. They also carry information about:
1) Whether they can be mapped cached.
2) Whether they are at all mappable.
3) Whether they need an ioremap to be accessible from kernel space.
In this way VRAM memory and, for example, pre-bound AGP appear
identical to the memory manager.
This also makes support for unmappable VRAM simple to implement.
2007-01-31 14:50:57 +01:00
ee4ac5c897
nouveau: determine chipset type at startup, instead of every time we use it.
2007-01-28 23:48:33 +11:00
c744bfde2d
make works ctx switch on nv10.
2007-01-26 21:57:44 +01:00
9c03ca81e7
nouveau: oops, wrong indexing in nv17 regs
2007-01-26 21:05:59 +01:00
5534c90ff3
nouveau: read gpu type once
2007-01-26 19:54:35 +01:00
05d3ed472e
nouveau: only save/restore nv17 regs on nv17,18 hw
2007-01-26 19:25:49 +01:00
e7ba15a003
nouveau: add extra pgraph registers
2007-01-26 19:24:34 +01:00
d4c9f135b5
nouveau: add some nv10 pgraph defines
2007-01-26 18:10:31 +01:00
6d9ef1a960
nouveau: simplify and fix BIG_ENDIAN flags
2007-01-25 23:06:48 +01:00
90ae39d2f0
nouveau: nv4c default context
2007-01-25 11:11:01 +11:00
aa7266385e
nouveau: always print nsource/nstatus regs on PGRAPH errors
2007-01-25 08:16:23 +11:00
7d4e6b1445
vblank interrupt fix
2007-01-24 16:33:21 +08:00
19ba074938
nouveau: fix getparam from 32-bit client on 64-bit kernel
2007-01-19 15:41:51 +11:00
4291df69bd
nouveau: re-add 6150 Go pciid (0x0244)
2007-01-19 15:16:18 +11:00
a40de938fa
nouveau: cleanup nv30_graph.c
2007-01-18 21:40:21 -05:00
ab72a7714e
nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching.
2007-01-18 21:40:21 -05:00
bd0418cb01
add missing quadro id
2007-01-18 17:35:28 +11:00
78a4f5c1bc
nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.
...
Hook into nv20 pgraph switching functions (they're identical for nv3x).
Actually call nv30_pgraph_context_init so the ctx_table is allocated.
Thanks to Carlos Martin for the help.
2007-01-17 08:46:59 -05:00
fdbc34fab0
nouveau: opps nv20 ctx ramin size was wrong
2007-01-14 20:04:20 +01:00
06cd155595
nouveau: opps restored the wrong channel
2007-01-13 23:30:43 +01:00
f04347f371
nouveau: nv20 graph ctx switch.
...
Untested...
2007-01-13 23:19:41 +01:00
cd5f543b2f
nouveau: first step to make graph ctx works
...
It is still not working, but now we could use some 3D commands
without needed to run nvidia blob before.
2007-01-13 21:44:50 +01:00
4ae64a1b58
nouveau: add and indent pgraph regs
2007-01-13 21:44:50 +01:00
1967aa82cf
nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value.
2007-01-13 12:32:50 +01:00
1bad7e0d02
nouveau : remove useless init : we clear RAMIN before
2007-01-12 20:31:18 +01:00
9d3deddc4a
Delay for a usec while spinning waiting for ring buffer space.
...
This means the loop will wait up to ~10ms for ring buffer space to become
available, rather than just however long it takes to check the space 10000
times. This matches other drivers' behavior when waiting for ring buffer/fifo
space.
2007-01-12 11:24:50 -08:00
4297a83b48
nouveau: get nv30 context switching to work.
...
* Pulled in some registers from nv10reg.h. Needed for context switching.
* Filled in nv30 graphics context (based on nv40_graph.c).
* Figure out nv30 context table, set up on context creation. Allows the cards automatic switching to work.
2007-01-12 00:14:54 -05:00
8ff026723c
radeon: Fix u32 overflows when determining AGP base address in card space.
...
The overflows could lead to the AGP aperture overlapping the framebuffer area
in the card's address space when the latter is located at the very end of the
32 bit address space, which would result in a freeze on X server startup,
probably because the card read commands from the framebuffer instead of from
AGP.
See http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=392915 .
2007-01-11 09:02:07 +01:00
a70aedd5fc
novueau: try resource 3 if resource 2 is 0 length
...
This happens on my NV43 PPC
2007-01-09 13:48:38 +11:00
deba42ef32
nouveau: fix nv4a context size.
2007-01-08 20:55:57 +01:00
d0080d71b9
nouveau: nv4a context support.
2007-01-08 05:02:40 +01:00
6eaa1272b4
Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm
2007-01-08 03:50:34 +01:00
26bf6d9b5b
nouveau: oops
2007-01-08 12:50:44 +11:00
128d87a3dd
nouveau: nv43 context stuff
2007-01-08 12:47:51 +11:00
1f0f7d7a18
nouveau: fix a stupid bug from me.
2007-01-08 00:11:39 +01:00
faa4612299
nouveau: avoid allocating vram that's used as instance memory.
2007-01-08 00:44:02 +11:00
cd3711455e
nouveau: map pci resource 2 on >=nv40
2007-01-08 00:44:02 +11:00
31daf66962
Revert i915 drm driver name to i915; miniglx doesn't work otherwise
...
Yes, this driver supports the new memory manager, that is indicated by the
version number being >= 1.7.
2007-01-06 17:40:50 -08:00
2851c9f5c6
Bump i915 minor for ARB_OC ioctl
2007-01-06 16:26:54 -08:00
f7180349fd
i915: ARB_Occlusion_query(MMIO ioctl) support.
...
This adds a new ioctl for passing counter information from the chip back to
applications, these counters include the data needed to perform OC.
2007-01-06 16:22:08 -08:00
1f1714cf3d
nouveau: get c51 doing glxgears without the binary driver's help.
2007-01-06 18:05:21 +11:00
dbb0d979cc
nouveau: Use PMC_BOOT_0 to determine which ctx_voodoo to load.
2007-01-06 17:50:00 +11:00
528ab8ce40
nouveau: oops, we don't need OS_HAS_MTRR actually.
2007-01-05 20:59:45 +01:00
d99c7c27e2
Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm
2007-01-05 20:50:46 +01:00
025f281bbf
nouveau: Add an mtrr over the whole FB
2007-01-05 20:49:34 +01:00
0f95ddc428
Merge branch 'master' of git+ssh://matc@git.freedesktop.org/git/mesa/drm/
2007-01-05 19:41:12 +01:00
9d167f1f4b
Add basic pgraph context for nv10.
...
It only fake a context switch : pgraph state are not save/restored.
2007-01-05 19:40:11 +01:00
f80659bc29
Cleanup the nv04 fifo code a bit.
2007-01-05 19:37:06 +01:00
4fe2858f53
i915: Fix a DRM_ERROR that should be DRM_DEBUG.
...
It would clutter up the kernel output in a situation which is legitimate before
X.org 7.2 and handled correctly by the 3D driver.
2007-01-02 10:05:48 +01:00
91855bb254
nouveau: oops, forgot to free RAMIN..
2007-01-02 16:35:00 +11:00
861017e6d5
nouveau: Hookup nv40_graph_init.
...
Now I can get 3D + working grctx switching on my NV40 without
the binary driver initialising the card first. However, this
change also breaks 3D on my C51 even *with* the binary driver's
help. So, it's likely that the weird voodoo is card-specific.
2007-01-02 15:56:10 +11:00
41da9fd2e5
nouveau: Hook up grctx code for NV4x.
...
This is enough to get grctx switching going on my NV40 and C51 after
the binary driver has initialised the card first.
Bumping the drm patchlevel because the ddx needs some modifications to
have NV4x work at all with these changes.
2007-01-02 15:08:04 +11:00
0e0d954584
nouveau: Add nv40-specific PGRAPH code, not hooked up yet.
2007-01-02 14:52:43 +11:00
2c3bc69ba2
nouveau: Only clobber PFIFO if no channels are already alloc'd
...
With this change the GPU is responsible for doing the channel switch
itself. This is needed for the upcoming NV4x PGRAPH context work as
we don't yet know enough to manually swap PGRAPH contexts.
2007-01-02 14:41:34 +11:00
a16a8a47cd
Add some new via chipsets.
...
Disable 3D functionality and AGP DMA for chipsets with the DX9 3D engine.
2006-12-28 22:17:08 +01:00
7859bd61d3
Leftover from previous commit.
2006-12-27 19:46:46 +01:00
2980ec22a1
Allow for non-power-of-two texture pitch alignment.
2006-12-27 19:38:33 +01:00
c38ede0667
nouveau: return the *actual* type of memory alloc'd to userspace
2006-12-27 01:58:57 +11:00
9e019df757
nouveau: Alloc cmdbuf for each channel individually
2006-12-26 23:30:26 +11:00
b7586ab539
nouveau: save/restore endianness flag on FIFO switch
...
This makes my G5 survive glxinfo and nouveau_demo - airlied
2006-12-21 17:47:10 +11:00
3b47b27558
Some via PCI posting flushes.
2006-12-20 13:04:21 +01:00
e5c4a26a29
Merge branch 'nouveau-1'
2006-12-20 10:30:16 +11:00
7458909bea
fixup i915 return values from kernel
2006-12-19 21:48:18 +11:00
07635f26a9
fix comment in r128
2006-12-19 17:58:20 +11:00
c52dea9a7d
fix some sizes in sis_drv.h
2006-12-19 17:58:16 +11:00
8cc82c5033
remove inline from large function
2006-12-19 17:58:12 +11:00
13659357ad
make a savage function static from kernel
2006-12-19 17:58:09 +11:00
cb280ad3c0
fix missing DRM_ERR from kernel
2006-12-19 17:58:03 +11:00
aefc7a3443
Unify radeon offset checking.
...
Replace r300_check_offset() with generic radeon_check_offset(), which doesn't
reject valid offsets when the framebuffer area is at the very end of the card's
32 bit address space. Make radeon_check_and_fixup_offset() use
radeon_check_offset() as well.
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=7697 .
2006-12-14 19:31:56 +01:00
1a40f3318c
Port remaining NV4 RAMIN access from the ddx into the drm.
...
Should fix lockups seen on NV4 cards.
2006-12-12 00:11:42 +11:00
Michel Dänzer
Ben Skeggs
Thomas Hellstrom
Eric Anholt
Stephane Marchesin
Matthieu Castet
Ben Skeggs
Patrice Mandin
Zou Nan hai
Jeremy Kolb
Dave Jones
Matthieu Castet
Haihao Xiang
Dave Airlie
Keith Packard
Wang Zhenyu
Ben Skeggs
Dave Airlie