Commit Graph

799 Commits (58b2ed78329305d5760c6df55175f958477f89ae)

Author SHA1 Message Date
Dave Airlie 2463b03cb4 whitespace cleanup pending a kernel merge 2007-03-19 08:23:43 +11:00
Nian Wu df73975980 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-14 17:00:27 +08:00
Oliver McFadden 93f66af76a r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; not
enough information is known about them to be sure as to what the values mean.
2007-03-13 14:48:01 +00:00
Nian Wu 80d0018bc0 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-13 17:00:31 +08:00
Oliver McFadden a90c2854a7 Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.
Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these
values are really unknown; ideally more reverse engineering should be done to
determine what these values mean and when they should be set.
2007-03-13 06:25:04 +00:00
Ben Skeggs 90f8c691a5 nouveau: make sure cmdbuf object gets destroyed 2007-03-13 14:55:54 +11:00
Ben Skeggs 1775202cf9 nouveau: associate all created objects with a channel + cleanups 2007-03-13 14:55:54 +11:00
Ben Skeggs 7e2bbe2954 nouveau: s/fifo/channel/ 2007-03-13 14:55:54 +11:00
Oliver McFadden 462a6ea4ca Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to either
R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values.
2007-03-13 01:19:56 +00:00
Oliver McFadden 5667396e05 Guess another unknown register used for R300 pacification. 2007-03-13 00:50:05 +00:00
Nian Wu ab75d50d6c Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-12 09:03:40 +08:00
Patrice Mandin 0cd5c650d1 nouveau: PUT,GET, not 2xPUT 2007-03-11 14:02:40 +01:00
Nian Wu b369724077 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-07 16:01:50 -05:00
Thomas Hellstrom 6ffe94f008 Add via CX700. 2007-03-07 09:19:57 +01:00
Nian Wu 0a85c9fa02 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-05 09:01:45 -05:00
Dave Airlie 188a93c9df radeon: make PCI GART aperture size variable, but making table size variable
This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0
2007-03-04 19:10:46 +11:00
Dave Airlie c9178c3d01 ati: make pcigart code able to handle variable size PCI GART aperture
This code doesn't enable a variable aperture it just modifies the codebase
to allow me fix it up later
2007-03-04 18:16:29 +11:00
Nian Wu 6c48b8e7ff Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-01 09:02:09 -05:00
Ben Skeggs 72caa48c82 nouveau: intrusive drm interface changes
graphics objects:
	- No longer takes flags/dmaobj parameters, requires some major changes
	  to the ddx to setup the object through the FIFO.  This change is
	  likely to cause breakages on some cards (tested on NV05,NV28,NV35,
	  NV40 and NV4E).
dma objects:
	- now takes a "class" parameter, not really used yet but we may need
	  it at some point.
	- parameters are checked, so clients can't randomly create DMA objects
	  pointing at whatever they feel like.
misc:
	- Added FB_SIZE/AGP_SIZE getparams
	- Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR
	- Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't
	  NOTIFICATION_PENDING.
2007-02-28 15:41:53 +11:00
Nian Wu df2fc3ec62 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-02-25 17:06:13 -08:00
Jakob Bornecrantz 9d8ba2d0d4 drm: remove unnecessary NULL checks, and fix some indents.. 2007-02-25 10:48:26 +11:00
Thomas Hellstrom e0f53e59be Simple fence object sample driver for via, based on idling the GPU.
Buffer object driver for via.
Some changes to buffer object driver callbacks.
Improve fence flushing.
2007-02-16 20:22:24 +01:00
Thomas Hellstrom 7766378d97 Initial support for fence object classes.
(Fence objects belonging to different command submission mechanisms).
2007-02-15 12:11:38 +01:00
Thomas Hellstrom a78f70faad Merge branch 'ttm-vram-0-1-branch' 2007-02-14 15:33:40 +01:00
Thomas Hellstrom 5c9a7b0f94 Remove an intel-specific hack and replace it with a fence driver callback. 2007-02-14 13:31:35 +01:00
Stephane Marchesin f524870184 nouveau: fix the build on big endian (thanks CyberFoxx) 2007-02-14 00:08:55 +01:00
B. Rathmann 59af900e4f nouveau: fix memory initialization with multiple cards. 2007-02-14 00:07:31 +01:00
Thomas Hellstrom e1460426b8 Bugzilla Bug #9457
Add refcounting of user waiters to the DRM hardware lock, so that we can use the
DRM_LOCK_CONT flag more conservatively.

Also add a kernel waiter refcount that if nonzero transfers the lock for the kernel context,
when it is released. This is useful when waiting for idle and can be used
for very simple fence object driver implementations for the new memory manager.

It also resolves the AIGLX startup deadlock for the sis and the via drivers.
i810, i830 still require that the hardware lock is really taken so the deadlock remains
for those two. I'm not sure about ffb. Anyone familiar with that code?
2007-02-13 20:47:30 +01:00
Wang Zhenyu 80095ffe01 i915: Add 965GM pci id update 2007-02-13 16:20:45 +08:00
Thomas Hellstrom abc14ddfb5 Update flags and comments. 2007-02-12 21:40:42 +01:00
Aapo Tahkola 130c39be3c Sync r300_reg.h from mesa driver. #10210 2007-02-11 10:24:14 +02:00
Michel Dänzer 4f795a05f1 Merge branch 'i915-pageflip' 2007-03-10 00:11:10 +01:00
Michel Dänzer d734992e6a i915: Only wait for pending flips before asynchronous flips again. 2007-03-10 00:10:49 +01:00
Michel Dänzer 0741064df4 i915: Do not wait for pending flips on both pipes at the same time.
The MI_WAIT_FOR_EVENT instruction does not support waiting for several events
at once, so this should fix the lockups with page flipping when both pipes are
enabled.
2007-03-09 16:39:13 +01:00
Ben Skeggs 1b3a6d4775 nouveau: remove a hack that's not needed since the last interface change. 2007-03-07 21:17:45 +11:00
Ben Skeggs 5bd0e52dba nouveau: ack PFIFO interrupts at PFIFO, not PMC. 2007-03-07 21:00:55 +11:00
Michel Dänzer a33859184a i915: Eliminate dev_priv->current_page.
Always use dev_priv->sarea_priv->pf_current_page directly. This allows clients
to modify it as well while they hold the HW lock, e.g. in order to sync pages
between pipes.
2007-02-28 17:48:56 +01:00
Michel Dänzer 074e10b384 i915: Only clean up page flipping when the last client goes away, not any one. 2007-02-28 15:57:08 +01:00
Michel Dänzer 1cdc1b6fba i915: Don't emit waits for pending flips before emitting synchronous flips.
The assumption is that synchronous flips are not isolated usually, and waiting
for all of them could result in stalling the pipeline for long periods of time.

Also use i915_emit_mi_flush() instead of an old-fashioned way to achieve the
same effect.
2007-02-28 15:23:19 +01:00
Michel Dänzer fd0fed3f1e i915: Fix test for synchronous flip affecting both pipes. 2007-02-28 12:33:56 +01:00
Michel Dänzer 1a0d890a42 i915: Add support for scheduled buffer swaps to be done as flips.
Unfortunately, emitting asynchronous flips during vertical blank results in
tearing. So we have to wait for the previous vertical blank and emit a
synchronous flip.
2007-02-22 17:21:18 +01:00
Michel Dänzer 5a40c043cc Add DRM_VBLANK_FLIP.
Used to request that a scheduled buffer swap be done as a flip instead of a
blit.
2007-02-22 17:19:30 +01:00
Michel Dänzer 6f89584e13 i915: Improved page flipping support, including triple buffering.
Pages are tracked independently on each pipe.

Bump the minor version for 3D clients to know page flipping is usable, and
bump driver date.
2007-02-19 15:08:40 +01:00
Michel Dänzer 34aa3393d0 i915: Page flipping enhancements.
Leave it to the client to wait for the flip to complete when necessary,
but wait for a previous flip to complete before emitting another one. This
should help avoid unnecessary stalling of the ring due to pending flips.

Call i915_do_cleanup_pageflip() unconditionally in preclose.
2007-02-19 15:08:40 +01:00
Michel Dänzer 078e430726 i915: Unify breadcrumb emission. 2007-02-19 15:08:40 +01:00
Thomas Hellstrom 53aee3122a I915 accelerated blit copy functional.
Fixed - to System memory copies are implemented by
flipping in a cache-coherent TTM,
blitting to it, and then flipping it out.
2007-02-09 16:36:53 +01:00
Eric Anholt 898aca1a66 Warning fix: correct type of i915_mmio argument. 2007-02-07 21:26:02 -08:00
Eric Anholt ef9a9d3cd1 Define __iomem for systems without it. 2007-02-07 21:26:01 -08:00
Eric Anholt 8918748058 Add chip family flags to i915 driver, and fix a missing '"' in mach64 ID list. 2007-02-07 21:26:01 -08:00
Thomas Hellstrom c1fbd8a566 Checkpoint commit.
Flag handling and memory type selection cleanup.
glxgears won't start.
2007-02-07 17:25:13 +01:00
Thomas Hellstrom 609e3b0375 Implement a policy for selecting memory types. 2007-02-06 14:20:33 +01:00
Stephane Marchesin 17985f07d6 nouveau: more work on the nv04 context switch code. 2007-02-06 01:17:32 +01:00
Stephane Marchesin 8c663b4e56 nouveau: and of course, I was missing the last nv04 piece. 2007-02-03 06:13:27 +01:00
Stephane Marchesin 0c13657c33 nouveau: plugin the nv04 graph init function. 2007-02-03 06:00:29 +01:00
Stephane Marchesin 7ab9e7f36f nouveau: cleanup the nv04 pgraph save/restore mechanism. 2007-02-03 05:56:42 +01:00
Stephane Marchesin d69902db3b nouveau: fix nv04 graph routines for new register names. 2007-02-03 05:25:36 +01:00
Stephane Marchesin 5a072f32c8 nouveau: rename registers to their proper names. 2007-02-03 04:57:06 +01:00
Stephane Marchesin e64dbef911 nouveau: add NV04 registers required for PGRAPH context switching. 2007-02-03 04:23:09 +01:00
Matthieu Castet 55f7859a25 nouveau: nv ctx switch opps the size of array was wrong 2007-02-02 23:01:03 +01:00
Matthieu Castet 63cf3b3da7 nouveau: nv10 ctx switch, some regs are nv17+ only 2007-02-02 20:08:33 +01:00
Thomas Hellstrom 6c04185857 via: Try to improve command-buffer chaining.
Bump driver date and patchlevel.
2007-02-02 09:22:30 +01:00
Thomas Hellstrom 70bba11bc7 Disable AGP DMA for chips with the new 3D engine. 2007-02-02 09:22:15 +01:00
Thomas Hellstrom 3024f23c65 memory manager: Make device driver aware of different memory types.
Memory types are either fixed (on-card or pre-bound AGP) or not fixed
(dynamically bound) to an aperture. They also carry information about:

1) Whether they can be mapped cached.
2) Whether they are at all mappable.
3) Whether they need an ioremap to be accessible from kernel space.

In this way VRAM memory and, for example, pre-bound AGP appear
identical to the memory manager.

This also makes support for unmappable VRAM simple to implement.
2007-01-31 14:50:57 +01:00
Ben Skeggs ee4ac5c897 nouveau: determine chipset type at startup, instead of every time we use it. 2007-01-28 23:48:33 +11:00
Matthieu Castet c744bfde2d make works ctx switch on nv10. 2007-01-26 21:57:44 +01:00
Patrice Mandin 9c03ca81e7 nouveau: oops, wrong indexing in nv17 regs 2007-01-26 21:05:59 +01:00
Patrice Mandin 5534c90ff3 nouveau: read gpu type once 2007-01-26 19:54:35 +01:00
Patrice Mandin 05d3ed472e nouveau: only save/restore nv17 regs on nv17,18 hw 2007-01-26 19:25:49 +01:00
Patrice Mandin e7ba15a003 nouveau: add extra pgraph registers 2007-01-26 19:24:34 +01:00
Patrice Mandin d4c9f135b5 nouveau: add some nv10 pgraph defines 2007-01-26 18:10:31 +01:00
Patrice Mandin 6d9ef1a960 nouveau: simplify and fix BIG_ENDIAN flags 2007-01-25 23:06:48 +01:00
Ben Skeggs 90ae39d2f0 nouveau: nv4c default context 2007-01-25 11:11:01 +11:00
Ben Skeggs aa7266385e nouveau: always print nsource/nstatus regs on PGRAPH errors 2007-01-25 08:16:23 +11:00
Zou Nan hai 7d4e6b1445 vblank interrupt fix 2007-01-24 16:33:21 +08:00
Ben Skeggs 19ba074938 nouveau: fix getparam from 32-bit client on 64-bit kernel 2007-01-19 15:41:51 +11:00
Ben Skeggs 4291df69bd nouveau: re-add 6150 Go pciid (0x0244) 2007-01-19 15:16:18 +11:00
Jeremy Kolb a40de938fa nouveau: cleanup nv30_graph.c 2007-01-18 21:40:21 -05:00
Jeremy Kolb ab72a7714e nouveau: Remove write to CTX_SIZE. This gives us proper nv3x PGRAPH switching. 2007-01-18 21:40:21 -05:00
Dave Jones bd0418cb01 add missing quadro id 2007-01-18 17:35:28 +11:00
Jeremy Kolb 78a4f5c1bc nouveau: Try to get nv35 pgraph switching working. Doesn't quite yet.
Hook into nv20 pgraph switching functions (they're identical for nv3x).
Actually call nv30_pgraph_context_init so the ctx_table is allocated.

Thanks to Carlos Martin for the help.
2007-01-17 08:46:59 -05:00
Matthieu Castet fdbc34fab0 nouveau: opps nv20 ctx ramin size was wrong 2007-01-14 20:04:20 +01:00
Matthieu Castet 06cd155595 nouveau: opps restored the wrong channel 2007-01-13 23:30:43 +01:00
Matthieu Castet f04347f371 nouveau: nv20 graph ctx switch.
Untested...
2007-01-13 23:19:41 +01:00
Matthieu Castet cd5f543b2f nouveau: first step to make graph ctx works
It is still not working, but now we could use some 3D commands
without needed to run nvidia blob before.
2007-01-13 21:44:50 +01:00
Matthieu Castet 4ae64a1b58 nouveau: add and indent pgraph regs 2007-01-13 21:44:50 +01:00
Stephane Marchesin 1967aa82cf nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value. 2007-01-13 12:32:50 +01:00
Matthieu Castet 1bad7e0d02 nouveau : remove useless init : we clear RAMIN before 2007-01-12 20:31:18 +01:00
Haihao Xiang 9d3deddc4a Delay for a usec while spinning waiting for ring buffer space.
This means the loop will wait up to ~10ms for ring buffer space to become
available, rather than just however long it takes to check the space 10000
times.  This matches other drivers' behavior when waiting for ring buffer/fifo
space.
2007-01-12 11:24:50 -08:00
Jeremy Kolb 4297a83b48 nouveau: get nv30 context switching to work.
* Pulled in some registers from nv10reg.h.  Needed for context switching.
* Filled in nv30 graphics context (based on nv40_graph.c).
* Figure out nv30 context table, set up on context creation.  Allows the cards automatic switching to work.
2007-01-12 00:14:54 -05:00
Michel Dänzer 8ff026723c radeon: Fix u32 overflows when determining AGP base address in card space.
The overflows could lead to the AGP aperture overlapping the framebuffer area
in the card's address space when the latter is located at the very end of the
32 bit address space, which would result in a freeze on X server startup,
probably because the card read commands from the framebuffer instead of from
AGP.

See http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=392915 .
2007-01-11 09:02:07 +01:00
Dave Airlie a70aedd5fc novueau: try resource 3 if resource 2 is 0 length
This happens on my NV43 PPC
2007-01-09 13:48:38 +11:00
Stephane Marchesin deba42ef32 nouveau: fix nv4a context size. 2007-01-08 20:55:57 +01:00
Stephane Marchesin d0080d71b9 nouveau: nv4a context support. 2007-01-08 05:02:40 +01:00
Stephane Marchesin 6eaa1272b4 Merge branch 'master' of git+ssh://marcheu@git.freedesktop.org/git/mesa/drm 2007-01-08 03:50:34 +01:00
Ben Skeggs 26bf6d9b5b nouveau: oops 2007-01-08 12:50:44 +11:00
Ben Skeggs 128d87a3dd nouveau: nv43 context stuff 2007-01-08 12:47:51 +11:00
Stephane Marchesin 1f0f7d7a18 nouveau: fix a stupid bug from me. 2007-01-08 00:11:39 +01:00
Ben Skeggs faa4612299 nouveau: avoid allocating vram that's used as instance memory. 2007-01-08 00:44:02 +11:00
Ben Skeggs cd3711455e nouveau: map pci resource 2 on >=nv40 2007-01-08 00:44:02 +11:00
Keith Packard 31daf66962 Revert i915 drm driver name to i915; miniglx doesn't work otherwise
Yes, this driver supports the new memory manager, that is indicated by the
version number being >= 1.7.
2007-01-06 17:40:50 -08:00