Commit Graph

2254 Commits (5fbdf9da8bda996c0a474d13fe69d260f12ffce7)

Author SHA1 Message Date
Arthur Huillet 5fbdf9da8b fixed object creation code to not Oops on 64bits, worked around memalloc not working on 64bit for PCIGART 2007-07-12 02:35:39 +02:00
Arthur Huillet b301a9051b NV50 will not attempt to use PCIGART now 2007-07-11 15:01:37 +02:00
Arthur Huillet d26ae22c2b fixed bug that prevented PCIE cards from actually using PCIGART - NV50 will probably still have a problem 2007-07-11 14:56:27 +02:00
Ben Skeggs 5ccadac9e3 nouveau/nv50: G80 fixes.
Again, no hardware, so no idea if it'll even work yet.  I understand how
the PRAMIN setup works now, un-hardcoding stuff will come "RealSoonNow(tm)".
2007-07-11 14:22:59 +10:00
Ben Skeggs 13e1377044 nouveau: Some checks on userspace object handles. 2007-07-11 12:39:30 +10:00
Arthur Huillet 694e1c5c3f Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel. 2007-07-11 02:35:10 +02:00
Arthur Huillet 04e4922c0c Made drm_sg_alloc accessible from inside the DRM - drm_sg_alloc_ioctl is the ioctl wrapper 2007-07-11 02:34:00 +02:00
Ben Skeggs 023f7d9c00 nouveau: Allocate mappable VRAM for notifiers.. 2007-07-09 23:58:00 +10:00
Ben Skeggs 31e33813e8 nouveau: Don't be so strict on <NV50 2007-07-09 20:02:14 +10:00
Ben Skeggs 3c58195ccd nouveau: Avoid oops
Turns out lastclose() gets called even if firstopen() has never been...
2007-07-09 16:16:44 +10:00
Ben Skeggs c806bba466 nouveau/nv50: Initial channel/object support
Should be OK on G84 for a single channel, multiple channels *almost* work.

Untested on G80.
2007-07-09 16:16:44 +10:00
Ben Skeggs 3324342e42 nouveau: enable reporting for all PFIFO/PGRAPH irqs 2007-07-09 16:16:44 +10:00
Ben Skeggs 163f852612 nouveau: rewrite gpu object code
Allows multiple references to a single object, needed to support PCI(E)GART
scatter-gather DMA objects which would quickly fill PRAMIN if each channel
had its own.

Handle per-channel private instmem areas.  This is needed to support NV50,
but might be something we want to do on earlier chipsets at some point?

Everything that touches PRAMIN is a GPU object.
2007-07-09 16:16:44 +10:00
Kristian Høgsberg d57b7f02d2 Use idr_replace trick to eliminate struct drm_ctx_sarea_list. 2007-07-03 10:41:48 -04:00
Kristian Høgsberg 1814a829eb Don't take dev->struct_mutex twice in drm_setsareactx. 2007-07-03 10:31:46 -04:00
Michel Dänzer 91990946fa One more spinlock initializer cleanup. 2007-07-03 12:33:51 +02:00
Michel Dänzer ea832a8e55 Simplification for previous commit.
Dave Airlie pointed out on IRC that idr_replace lets us know if the ID hasn't
been allocated, so we don't need a special pointer value for allocated IDs that
don't have valid information yet.
2007-07-03 12:15:15 +02:00
Michel Dänzer 8d96ba9805 Restore pre-idr semantics for drawable information.
There's a difference between a drawable ID not having valid drawable
information and not being allocated at all. Not making the distinction would
break i915 DRM swap scheduling with older X servers that don't push drawable
cliprect information to the DRM.
2007-07-03 11:41:44 +02:00
Kristian Høgsberg c9d752ff4f Fix must-check warnings and implement a few error paths. 2007-07-02 17:52:07 -04:00
Kristian Høgsberg b323ab52aa Drop drm_drawable_list and add drm_drawable_info directly to the idr. 2007-07-02 15:07:02 -04:00
Thomas Hellstrom a27af4c4a6 Avoid hitting BUG() for kernel-only fence objects. 2007-06-29 15:22:28 +02:00
Thomas Hellstrom 00f1a66f22 Fence object reference / dereference cleanup.
Buffer object dereference cleanup.
Add a struct drm_device member to fence objects:
This can simplify code, particularly in drivers.
2007-06-29 12:58:45 +02:00
Ben Skeggs e26ec51146 nouveau: small RAMFC cleanups 2007-06-29 14:20:50 +10:00
Ben Skeggs 1c32fecd6d nouveau: Hack around possible Xv blit adaptor breakage 2007-06-28 21:01:17 +10:00
Ben Skeggs 2dd85772aa nouveau/nv10: Fix earlier NV1x chips
Can't use nv04 code for them, since an extra field was inserted into
RAMFC after DMA_PUT/GET.
2007-06-28 04:23:17 +10:00
Ben Skeggs 68ecf61647 nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bit 2007-06-28 03:26:44 +10:00
Ben Skeggs 18a6d1c9c3 nouveau: simplify PRAMIN access 2007-06-28 03:26:44 +10:00
Ben Skeggs 38617b6a26 nouveau: name some regs 2007-06-28 03:26:44 +10:00
Ben Skeggs ce0d528d3c nouveau/nv50: skeletal backend 2007-06-28 03:26:43 +10:00
Ben Skeggs 695599f18d nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)
For various reasons, this ioctl was a bad idea.

At channel creation we now automatically create DMA objects covering
available VRAM and GART memory, where the client used to do this themselves.

However, there is still a need to be able to create DMA objects pointing at
specific areas of memory (ie. notifiers).  Each channel is now allocated a
small amount of memory from which a client can suballocate things (such as
notifiers), and have a DMA object created which covers the suballocated area.
The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-28 03:26:43 +10:00
Ben Skeggs 4f2dd78ff3 nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaks 2007-06-28 03:04:48 +10:00
Ian Romanick 5c27f8a70e Add support SiS based XGI chips to SiS DRM. 2007-06-26 09:51:55 -07:00
Ben Skeggs 9f617522d9 nouveau: NV49/NV4B PGRAPH setup from jb17bsome and stephan_2303 2007-06-25 01:57:57 +10:00
Ben Skeggs 3dfc13e2da nouveau: kill some dead code 2007-06-24 19:00:44 +10:00
Ben Skeggs 5f05cd7086 nouveau: NV04/NV10/NV20 PGRAPH engtab functions
NV04/NV10 load_context()/save_context() are stubs.  I don't know enough about
how they work to implement them sanely.  The "old" context_switch() code
remains hooked up, so it shouldn't break anything.

NV20 will probably break if load_context() works.  No inital context values
are filled in, so when the first channel is created PGRAPH will probably end
up having its state zeroed.  Some setup from nv20_graph_init() will probably
need to be moved to the per-channel context setup.
2007-06-24 19:00:26 +10:00
Ben Skeggs 5d55b0655c nouveau: NV3X PGRAPH engtab functions 2007-06-24 18:58:38 +10:00
Ben Skeggs 341bc78207 nouveau: NV1X/2X/3X PFIFO engtab functions
Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC
entry size.
2007-06-24 18:58:14 +10:00
Ben Skeggs 05d86d950a nouveau: NV04 PFIFO engtab functions 2007-06-24 18:57:09 +10:00
Ben Skeggs acb710d1a5 nouveau: NV4X PGRAPH engtab functions 2007-06-24 18:56:40 +10:00
Ben Skeggs f2e64d5276 nouveau: NV4X PFIFO engtab functions 2007-06-24 18:56:01 +10:00
Ben Skeggs 0afb3b518e nouveau: split PFIFO/PGRAPH context creation 2007-06-24 18:55:23 +10:00
Ben Skeggs 9dbf322d26 nouveau: (mostly) hook up put_base again 2007-06-24 18:55:06 +10:00
Ben Skeggs 24b71c318a nouveau: prototype PFIFO/PGRAPH engtab API 2007-06-24 18:54:51 +10:00
Ben Skeggs 5c7c07fd49 nouveau: rename engtab functions 2007-06-24 18:54:36 +10:00
Michel Dänzer 068ffc1e1b radeon: Acknowledge all interrupts we're interested in.
Failure to do so was probably the root cause of fd.o bug 11287.
2007-06-22 11:55:26 +02:00
Oliver McFadden 40f6a696cb r300: Synchronized the register defines file; documentation changes. 2007-06-21 14:35:11 +00:00
Oliver McFadden 213732af43 r300: Allow writes to R300_VAP_PVS_WAITIDLE. 2007-06-21 14:32:58 +00:00
Oliver McFadden 215787e429 r300: Registers 0x2220-0x2230 are known as R300_VAP_CLIP_X_0-R300_VAP_CLIP_Y_1. 2007-06-18 08:42:46 +00:00
Oliver McFadden 8038e7b60f r300: Synchronized the register defines file again. 2007-06-18 08:36:50 +00:00
David Woodhouse 638ebbab54 fix radeon setparam on 32/64 systems, harder.
Commit 9b01bd5b284bbf519b726b39f1352023cb5e9e69 introduced a
    compat_ioctl handler for RADEON_SETPARAM, the sole purpose of which was
    to handle the fact that on i386, alignof(uint64_t)==4.

    Unfortunately, this handler was installed for _all_ 64-bit
    architectures, instead of only x86_64 and ia64.  And thus it breaks
    32-bit compatibility on every other arch, where 64-bit integers are
    aligned to 8 bytes in 32-bit mode just the same as in 64-bit mode.

    Arnd has a cunning plan to use 'compat_u64' with appropriate alignment
    attributes according to the 32-bit ABI, but for now let's just make the
    compat_radeon_cp_setparam routine entirely disappear on 64-bit machines
    whose 32-bit compat support isn't for i386.  It would be a no-op with
    compat_u64 anyway.

    Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2007-06-18 12:46:00 +10:00