Simplifies its callers.
dev->bo_table_mutex is now always held when amdgpu_bo_create is called
(this was already the case in amdgpu_bo_import).
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
And propagate drmIoctl's return value.
This allows replacing all remaining open-coded DRM_IOCTL_GEM_CLOSE
ioctl calls with amdgpu_close_kms_handle calls.
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
The following situation can happen in a multithreaded OpenGL application.
A BO is submitted from etna_cmd_stream #1 with flags set for read.
A BO is submitted from etna_cmd_stream #2 with flags set for write.
This triggers a flush on stream #1 and clears the BO's current_stream
pointer. If at this point, stream #2 attempts to queue BO again, which
does happen, the BO will be added to the submit list twice. The Linux
kernel driver correctly detects this and warns about it with "BO at
index %u already on submit list" kernel message.
However, when cleaning the BO cache in etna_bo_cache_free(), the BO
which was submitted twice will also be free()d twice, this triggering
a glibc double free detector.
The fix is easy, even if the BO does not have current_stream set,
iterate over current streams' list of BOs before adding the BO to it
and verify that the BO is not yet there.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Wladimir J. van der Laan <laanwj@gmail.com>
Avoids compiler warning:
../../amdgpu/amdgpu_cs.c: In function 'amdgpu_cs_ctx_override_priority':
../../amdgpu/amdgpu_cs.c:155:2: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
union drm_amdgpu_sched args;
^~~~~
Reviewed-by: Christian König <christian.koenig@amd.com>
There is no implementation and also no users, so there is no point
in keeping it in the API.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Instead of hacking the binary every time, we can now specify directly.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
This includes logic to configure the LUT accordingly.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
As new features are added and others are declared to be legacy, it's
nice to be able to implement fallbacks. As such, create a
property-setting variant that does not generate errors which can very
well be entirely expected.
Will be used for gamma control in a future change.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
This change adds support for all current patterns.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
The idea is to have a horizontal pattern split into two with the top and
bottom halves having different precision. This allows one to see whether
10bpc support is working properly or not, as there are many pieces to
the puzzle beyond the basic format support (gamma ramps, bpc encodings,
etc).
This is really only useful on 10bpc formats, but we also add support for
8bpc formats to ease testing. In the future, this could be applied to
16bpc formats as well.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
We need to shift the values up, otherwise we'd end up with a negative
shift. This works for up-to 16-bit components, which is fine for now.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
This also adds a helper to generate a color LUT, which has to be used in
conjunction with the C8 indexed format.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
With different register offsets from VCN1.0
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
AMDGPU_VRAM_TYPE_GDDR6 is a new vram type for navi10
Reviewed-by: Tim Writer <Tim.Writer@amd.com>
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
pa_sc_tile_steering_override is a new member introduced for gfx10
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Feature is controlled by DRM_CAP_SYNCOBJ_TIMELINE drm capability.
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
a) delta: only DRM_CAP_SYNCOBJ_TIMELINE
b) Generated using make headers_install.
c) Generated from origin/drm-misc-next commit 982c0500fd1a8012c31d3c9dd8de285129904656"
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Suggested-by: Michel Dänzer <michel@daenzer.net>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
v2: drop DRM_SYNCOBJ_CREATE_TYPE_TIMELINE, fix timeout calculation,
fix some warnings
v3: add export/import and cpu signal testing cases
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
v2: adapt to new one transfer ioctl
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
v2: symbos are stored in lexical order.
v3: drop export/import and extra query indirection
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
In drmModeGetPropertyPtr(), from upper error path, it calls free
but with just next error path, it does not call. Fix the possible
memory leak.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
The pointer p aquired with drmModeGetPlane() is not free in error
path. Fix possible memory leak by calling drmModeFreePlane() in
the error path.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Allows mmap on dmabuf fd with MAP_SHARED and PROT_WRITE.
This fixes boot failures with Android (likely w/ closed source
user-space drivers) that were caused due to mmap() returning
error.
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Hemant Hariyani <hemanthariyani@ti.com>
[picked and updated commitmsg from http://git.ti.com/cgit/cgit.cgi/android/external-libdrm.git/]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Alistair Strachan <astrachan@google.com>
[jstultz: Tweaked commit message]
Signed-off-by: John Stultz <john.stultz@linaro.org>
When calling drmModeAtomicAddProperty allocation of memory
happens as needed in increments of 16 elements. This can be very
slow if there are multiple properties to be updated in an Atomic
Commit call.
Increase this to as many as can fit in a memory PAGE to avoid
having to reallocate memory too often.
Also this patch has a small one line perf tweak in
drmModeAtomicDuplicate() to only memcpy items to the cursor
position in order avoid copying the entire item array if its
mostly empty.
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[jstultz: Expanded commit message]
Signed-off-by: John Stultz <john.stultz@linaro.org>
Avoid additional drm device open and close.
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Clang complains when initializing unions using "= {0}"
so instead use memset.
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
__mmap2 isn't supported on all platforms, mmap64 is the right way
to do this in android.
Also folds in a fix from Stéphane Marchesin <marcheu@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
[jstultz: Folded in Stéphane's fix]
Signed-off-by: John Stultz <john.stultz@linaro.org>
Add a check to error out on Android version K(4.4) or
lower.
This is due to dependency added in a previous commit on mmap64,
which was introduced with Android L.
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Marissa Wall <marissaw@google.com>
Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
This way we can override the priority of a single context using a
master fd.
Since we cannot usefully create an amdgpu device of a master fd
without the fd deduplication kicking in this takes a plain fd.
This can be used by e.g. radv to get high priority contexts using
a master fd from the primary node or a lease.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
This makes the test utilities work with the Armada driver without the
necessity of using the -M argument.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
This reverts commit 56c21f877b.
There were issues pointed out during review that were not addressed.
Would love to have this re-land, once those are addressed.
Saw a couple of typos fixes in the patch DragonFlyBSD carries [1], so
I ran codespell (a spell checker for code) on the whole repo.
[1] https://github.com/DragonFlyBSD/DPorts/blob/master/graphics/libdrm/files/patch-xf86drm.c
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
struct drmPciBusInfo has been aligned to 6 bytes. So memcmp will access
the last byte which is not initialized.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Generated using make headers_install from the drm-next
tree - git://anongit.freedesktop.org/drm/drm
branch - drm-next
commit - 14d2bd53a47a7e1cb3e03d00a6b952734cf90f3f
The changes were as follows :-
core: (drm.h, drm_fourcc.h, drm_mode.h)
- Added 'struct drm_syncobj_transfer', 'struct drm_syncobj_timeline_wait' and 'struct drm_syncobj_timeline_array'
- Added various DRM_IOCTL_SYNCOBJ_ ioctls
- Added some new RGB and YUV formats
- Added 'DRM_FORMAT_MOD_VENDOR_ALLWINNER'
- Added 'SAMSUNG' and Arm's 'AFBC' and 'ALLWINNER' format modifiers
- Added 'struct drm_mode_rect'
i915:
- Added struct 'struct i915_user_extension' and various 'struct drm_i915_gem_context_'
- Added different modes of per-process Graphics Translation Table
Changes from v1:-
- Removed the changes to 'msm_drm.h' as it breaks the build for 'freedreno' platform.
Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
support per device test mask. Skip inject test on non-server card.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>