caace3692f
RS4xx: separate out RS400 and RS480 IGP chips
...
RS400 (intel based IGP) and RS480 (AMD based IGP) have
different MC and GART setups. Currently we only support
RS480.
2008-05-13 21:02:17 -04:00
10d754f0a2
RADEON: fix copy/pasto in last commit
2008-05-12 14:49:43 -04:00
75bc739bee
R3/4/5: init pipe setup in drm
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Similar (broken) code in mesa needs to be removed
2008-05-12 09:44:20 -04:00
e16a7101e8
RADEON: cleanup radeon_do_engine_reset()
2008-05-12 09:35:06 -04:00
5532b8d2a0
R300+: fixup pixcache flush
2008-05-12 09:30:47 -04:00
3582e82f14
RS4xx: fix MCIND index mask
2008-05-12 09:24:13 -04:00
d26af273f8
RADEON: write AGP_BASE_2 on chips that support it
2008-05-12 09:21:45 -04:00
c307e50724
R300+: fixup PURGE/FLUSH macros
2008-05-12 09:18:28 -04:00
fb9eaff747
Radeon IGP: merge RS4xx/RS6xx gart setup
2008-05-12 09:13:44 -04:00
68b7f550ba
Radeon IGP: wrap MCIND access
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first step in merging rs4xx/rs6xx gart setup
2008-05-12 09:00:40 -04:00
a34025ce22
Radeon IGP: clean up registers and magic numbers
2008-05-12 08:56:11 -04:00
d015219bd0
r500: add allowed range for us config/pixsize
2008-05-05 17:03:27 +10:00
3ac74f3208
nv50: enable 0x400500 bit 0 after PGRAPH exception also
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No solid idea about what these 2 bits do, but nv50 can now survive a few
PGRAPH exceptions just as nv40 does :)
2008-05-02 01:36:30 +10:00
6d8062ac1e
nouveau: guard against channels potentially not having a context, fix nv50
2008-05-02 01:36:08 +10:00
77d20928b3
nouveau: disable all card interrupts when unknown PFIFO IRQ occurs.
...
This is possibly temporary. I can trigger an unending IRQ storm on G8x
in some circumstances, and have no idea how to handle that particular PFIFO
exception correctly yet.
2008-05-02 00:53:42 +10:00
5c4c778c0d
nouveau: restore original NV_PFIFO_CACHES_REASSIGN value in fifo handler
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Doesn't fix any issue I've seen, but is a potential issue if a FIFO IRQ
occurs during channel creation/takedown.
2008-05-02 00:52:21 +10:00
bfbe4ade32
nouveau: gather nsource in trap_info()
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The IRQ handling stuff really is a mess.. On the TODO :)
2008-05-02 00:51:00 +10:00
e317dfdabf
nv50: PGRAPH exception handling completely different from earlier chips
2008-05-02 00:06:22 +10:00
b92efd5956
nv50: I cave... Add nv84 initial context values.
...
I swore I'd actually do this properly and not go the horrible route
we did with nv4x, but I won't get around to it just yet with so many
*actually* interesting things to do first.. One day.
Since someone already added nv86, why not!
2008-05-01 23:50:44 +10:00
cb33133ef3
i915: fix off by one in VGA save/restore of AR & CR regs
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Turns out it's important to save/restore AR14 in particular.
2008-04-29 12:39:38 -07:00
f31e04a960
nouveau: NV9x cards exist as well.
2008-04-29 19:34:22 +02:00
7f8e406085
Use fixed sized types in new ioctls
...
Make both crtc and the command argument 32 bits to avoid any 32-on-64 compat
issues.
2008-04-27 09:42:17 -07:00
b45fe49bcd
Enum-ectomy of vblank modesetting ioctl
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Enum can be of pretty much any size since C leaves the choice of size up to the implementation. So avoid using it in new interfaces like the vblank pre- & post-modeset ioctl. Thanks to hch for spotting this.
2008-04-26 17:11:18 -07:00
feff72929e
i915: fix for compatibility mode
2008-04-23 17:17:16 +08:00
ce8c842518
i915: gfx hw and i945gme fixes from upstream
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From Jesse and Zhenyu originally.
2008-04-22 16:08:17 +10:00
f0e38f5217
[I915] Handle tiled buffers in vblank tasklet
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The vblank tasklet update code must build 2D blt commands with the
appropriate tiled flags.
2008-04-20 16:10:05 -07:00
21dbba5a22
On I965, use correct 3DSTATE_DRAWING_RECTANGLE command in vblank
...
The batchbuffer submission paths were fixed to use the 965-specific command,
but the vblank tasklet was not. When the older version is sent, the 965 will
lock up.
2008-04-20 01:56:02 -07:00
b986d7d2c9
Save and restore dsparb and d_state regs
2008-04-11 20:31:07 -07:00
1692d30cea
nv50: primitive i2c interrupt handler
2008-04-05 21:02:00 +02:00
3fc444a5e8
nv50: primitive display interrupt handler.
2008-04-03 01:13:31 +02:00
562f95ea96
nouveau: fix return from function..
...
dude kernel moduless use kernel errors :)
this fixes an oops on init when this codepath hits.
2008-03-31 11:34:48 +10:00
cf3c0123a0
nouveau: forgot to add a break
2008-03-30 14:50:41 +02:00
68b83a8813
nouveau: Add ctx values for nv86.
...
- Note that this may not work for all nv86.
2008-03-30 14:48:55 +02:00
753a4bdf1b
drm/r300: fix wait interface mixup
...
This interface was defined completely wrong, however userspace has only
ever used 4 values from it (0x1, 0x2, 0x3 and 0x6), so fix the interface to do what userspace actually expected but define new defines for new users to use
it properly.
2008-03-30 07:33:39 +10:00
1674d28179
r300: Correctly translate the value for the R300_CMD_WAIT command.
...
Previously, the R300_CMD_WAIT command would write the passed directly to the
hardware. However this is incorrect because the R300_WAIT_* values used are
internal interface values that do not map directly to the hardware.
The new function I have added translates the R300_WAIT_* values into appropriate
values for the hardware before writing the register.
Thanks to John Bridgman for pointing this out. :-)
2008-03-29 17:31:39 +00:00
a81d07f64d
nouveau: nv20 bios does not initialise PTIMER
...
The wait functions depend on PTIMER, so write the old (incorrect, but working) values for uninitialised hw
2008-03-25 18:32:26 +00:00
b0817a42e7
i915: fix oops on agp=off
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Kernel bug 10289.
2008-03-24 18:52:26 +10:00
4323ee3e5b
Merge branch 'r500-fp'
2008-03-24 18:47:50 +10:00
24ba0c9c3b
nv40: voodoo - not quite.
2008-03-24 03:26:34 +11:00
6f4b3de284
nv40: allocate massive amount of PRAMIN for grctx on all chipsets.
...
More or less a workaround for issues on some chipsets where a context
switch results in critical data in PRAMIN being overwritten by the GPU.
The correct fix is known, but may take some time before it's a feasible
option.
2008-03-24 03:26:30 +11:00
36e11dd380
r500: fragment program upload is also used to upload constants.
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Limit frag address to 8 bits
2008-03-21 16:59:52 +10:00
316979356f
drm: fixup r500fp submission
2008-03-20 14:20:53 +10:00
1021799b6c
nouveau: do not set on-board timer's numerator/denominator to bad values
2008-03-20 02:57:58 +00:00
9e4f908287
RADEON: switch over to new production microcode
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This needs to be tested thoroughly before pushing to the
kernel.
2008-03-19 15:37:56 -04:00
d8af16d2a7
RADEON: production microcode for all radeons, r1xx-r6xx
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This updated microcode is not in use yet.
2008-03-19 14:57:42 -04:00
a3c808d8fe
move some more r300 regs into not allowed on r500
2008-03-19 16:10:37 +10:00
d18c2c6842
drm: add new rs690 pci id
2008-03-18 09:07:45 +10:00
3add949403
initial r500 RS and FP register and upload code
2008-03-17 11:08:03 +10:00
1f96e9a982
drm/pcigart: fix the pci gart to use the drm_pci wrapper.
...
This is the correct fix for the RS690 and hopefully the dma coherent work.
For now we limit everybody to a 32-bit DMA mask but it is possible for
RS690 to use a 40-bit DMA mask for the GART table itself,
and the PCIE cards can use 40-bits for the table entries.
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-03-17 07:05:46 +10:00
1a2d8c4bfa
Avoid unnecessary waits for command regulator pause.
2008-03-16 20:07:14 +01:00
Alex Deucher
Dave Airlie
Ben Skeggs
Jesse Barnes
Maarten Maathuis
Jesse Barnes
Jesse Barnes
Xiang, Haihao
Dave Airlie
Keith Packard
Oliver McFadden
Stuart Bennett
Alex Deucher
Thomas Hellstrom