f6982b54c9
RADEON: switch IGP gart to use radeon_write_agp_base()
2008-06-09 16:28:35 -04:00
63eb58040d
Fix typo in i915_suspend
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Reported by vehemens
2008-06-08 23:46:14 -04:00
116870a908
I915 suspend/resume for FreeBSD
2008-06-08 13:56:14 -04:00
d43f3cb097
r300/r500: add hier-z regs
2008-06-09 05:32:41 +10:00
6905c7a29d
radeon: Restore software interrupt on resume.
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Fixes performance drop after suspend/resume on some systems.
2008-06-05 18:23:37 +02:00
d5ae19ebcf
drm: sg alloc should write back the handle to userspace
2008-06-03 12:44:06 +10:00
a12cbf8aa5
RADEON: fix typo in last commit
2008-05-30 18:20:01 -04:00
6e8a2cff66
r500: attempt to make AGP work by programming agp base in the MC correctly
2008-05-30 20:27:31 +10:00
5b86823fa3
radeon: split microcode out into a separate header file.
2008-05-28 11:12:57 +10:00
0c8a8db1b6
i915: fix BSD bh, DRI2 not uses anywhere else
2008-05-28 10:28:13 +10:00
c06096d34f
radeon: bump release date/version for r500 3D support
2008-05-28 10:02:20 +10:00
59c953245c
RADEON: add get_param for number of GB pipes
2008-05-27 18:34:33 -04:00
e45f95a03b
[i915] Fix typo in (unused) START_ADDR definition.
2008-05-27 14:55:01 -07:00
8cd045079e
[FreeBSD] Add vblank-rework support and get drivers building.
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The i915 driver now works again.
2008-05-27 14:25:20 -07:00
49075b678f
r500: add two more register ranges for mesa driver to setup
2008-05-23 09:40:26 +10:00
74a9ea896e
drm: fix nouveau warning
2008-05-23 09:40:26 +10:00
91c6c4b240
rs690/r500: vblank support.
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The new display controller has the vblank interrupts in a different place.
Add support for vbl interrupts for these chips
2008-05-21 21:27:33 +10:00
8399656106
r500: add more register ranges for Mesa driver
2008-05-17 10:22:12 +10:00
caace3692f
RS4xx: separate out RS400 and RS480 IGP chips
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RS400 (intel based IGP) and RS480 (AMD based IGP) have
different MC and GART setups. Currently we only support
RS480.
2008-05-13 21:02:17 -04:00
10d754f0a2
RADEON: fix copy/pasto in last commit
2008-05-12 14:49:43 -04:00
75bc739bee
R3/4/5: init pipe setup in drm
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Similar (broken) code in mesa needs to be removed
2008-05-12 09:44:20 -04:00
e16a7101e8
RADEON: cleanup radeon_do_engine_reset()
2008-05-12 09:35:06 -04:00
5532b8d2a0
R300+: fixup pixcache flush
2008-05-12 09:30:47 -04:00
3582e82f14
RS4xx: fix MCIND index mask
2008-05-12 09:24:13 -04:00
d26af273f8
RADEON: write AGP_BASE_2 on chips that support it
2008-05-12 09:21:45 -04:00
c307e50724
R300+: fixup PURGE/FLUSH macros
2008-05-12 09:18:28 -04:00
fb9eaff747
Radeon IGP: merge RS4xx/RS6xx gart setup
2008-05-12 09:13:44 -04:00
68b7f550ba
Radeon IGP: wrap MCIND access
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first step in merging rs4xx/rs6xx gart setup
2008-05-12 09:00:40 -04:00
a34025ce22
Radeon IGP: clean up registers and magic numbers
2008-05-12 08:56:11 -04:00
d015219bd0
r500: add allowed range for us config/pixsize
2008-05-05 17:03:27 +10:00
3ac74f3208
nv50: enable 0x400500 bit 0 after PGRAPH exception also
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No solid idea about what these 2 bits do, but nv50 can now survive a few
PGRAPH exceptions just as nv40 does :)
2008-05-02 01:36:30 +10:00
6d8062ac1e
nouveau: guard against channels potentially not having a context, fix nv50
2008-05-02 01:36:08 +10:00
77d20928b3
nouveau: disable all card interrupts when unknown PFIFO IRQ occurs.
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This is possibly temporary. I can trigger an unending IRQ storm on G8x
in some circumstances, and have no idea how to handle that particular PFIFO
exception correctly yet.
2008-05-02 00:53:42 +10:00
5c4c778c0d
nouveau: restore original NV_PFIFO_CACHES_REASSIGN value in fifo handler
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Doesn't fix any issue I've seen, but is a potential issue if a FIFO IRQ
occurs during channel creation/takedown.
2008-05-02 00:52:21 +10:00
bfbe4ade32
nouveau: gather nsource in trap_info()
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The IRQ handling stuff really is a mess.. On the TODO :)
2008-05-02 00:51:00 +10:00
e317dfdabf
nv50: PGRAPH exception handling completely different from earlier chips
2008-05-02 00:06:22 +10:00
b92efd5956
nv50: I cave... Add nv84 initial context values.
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I swore I'd actually do this properly and not go the horrible route
we did with nv4x, but I won't get around to it just yet with so many
*actually* interesting things to do first.. One day.
Since someone already added nv86, why not!
2008-05-01 23:50:44 +10:00
cb33133ef3
i915: fix off by one in VGA save/restore of AR & CR regs
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Turns out it's important to save/restore AR14 in particular.
2008-04-29 12:39:38 -07:00
f31e04a960
nouveau: NV9x cards exist as well.
2008-04-29 19:34:22 +02:00
7f8e406085
Use fixed sized types in new ioctls
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Make both crtc and the command argument 32 bits to avoid any 32-on-64 compat
issues.
2008-04-27 09:42:17 -07:00
b45fe49bcd
Enum-ectomy of vblank modesetting ioctl
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Enum can be of pretty much any size since C leaves the choice of size up to the implementation. So avoid using it in new interfaces like the vblank pre- & post-modeset ioctl. Thanks to hch for spotting this.
2008-04-26 17:11:18 -07:00
feff72929e
i915: fix for compatibility mode
2008-04-23 17:17:16 +08:00
ce8c842518
i915: gfx hw and i945gme fixes from upstream
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From Jesse and Zhenyu originally.
2008-04-22 16:08:17 +10:00
f0e38f5217
[I915] Handle tiled buffers in vblank tasklet
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The vblank tasklet update code must build 2D blt commands with the
appropriate tiled flags.
2008-04-20 16:10:05 -07:00
21dbba5a22
On I965, use correct 3DSTATE_DRAWING_RECTANGLE command in vblank
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The batchbuffer submission paths were fixed to use the 965-specific command,
but the vblank tasklet was not. When the older version is sent, the 965 will
lock up.
2008-04-20 01:56:02 -07:00
b986d7d2c9
Save and restore dsparb and d_state regs
2008-04-11 20:31:07 -07:00
1692d30cea
nv50: primitive i2c interrupt handler
2008-04-05 21:02:00 +02:00
3fc444a5e8
nv50: primitive display interrupt handler.
2008-04-03 01:13:31 +02:00
562f95ea96
nouveau: fix return from function..
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dude kernel moduless use kernel errors :)
this fixes an oops on init when this codepath hits.
2008-03-31 11:34:48 +10:00
cf3c0123a0
nouveau: forgot to add a break
2008-03-30 14:50:41 +02:00
Alex Deucher
Robert Noland
Dave Airlie
Dennis Kasprzyk
Dave Airlie
Alex Deucher
Jie Luo
Robert Noland
Alex Deucher
Ben Skeggs
Jesse Barnes
Maarten Maathuis
Jesse Barnes
Jesse Barnes
Xiang, Haihao
Keith Packard