49075b678f
r500: add two more register ranges for mesa driver to setup
2008-05-23 09:40:26 +10:00
74a9ea896e
drm: fix nouveau warning
2008-05-23 09:40:26 +10:00
91c6c4b240
rs690/r500: vblank support.
...
The new display controller has the vblank interrupts in a different place.
Add support for vbl interrupts for these chips
2008-05-21 21:27:33 +10:00
8399656106
r500: add more register ranges for Mesa driver
2008-05-17 10:22:12 +10:00
caace3692f
RS4xx: separate out RS400 and RS480 IGP chips
...
RS400 (intel based IGP) and RS480 (AMD based IGP) have
different MC and GART setups. Currently we only support
RS480.
2008-05-13 21:02:17 -04:00
10d754f0a2
RADEON: fix copy/pasto in last commit
2008-05-12 14:49:43 -04:00
75bc739bee
R3/4/5: init pipe setup in drm
...
Similar (broken) code in mesa needs to be removed
2008-05-12 09:44:20 -04:00
e16a7101e8
RADEON: cleanup radeon_do_engine_reset()
2008-05-12 09:35:06 -04:00
5532b8d2a0
R300+: fixup pixcache flush
2008-05-12 09:30:47 -04:00
3582e82f14
RS4xx: fix MCIND index mask
2008-05-12 09:24:13 -04:00
d26af273f8
RADEON: write AGP_BASE_2 on chips that support it
2008-05-12 09:21:45 -04:00
c307e50724
R300+: fixup PURGE/FLUSH macros
2008-05-12 09:18:28 -04:00
fb9eaff747
Radeon IGP: merge RS4xx/RS6xx gart setup
2008-05-12 09:13:44 -04:00
68b7f550ba
Radeon IGP: wrap MCIND access
...
first step in merging rs4xx/rs6xx gart setup
2008-05-12 09:00:40 -04:00
a34025ce22
Radeon IGP: clean up registers and magic numbers
2008-05-12 08:56:11 -04:00
d015219bd0
r500: add allowed range for us config/pixsize
2008-05-05 17:03:27 +10:00
3ac74f3208
nv50: enable 0x400500 bit 0 after PGRAPH exception also
...
No solid idea about what these 2 bits do, but nv50 can now survive a few
PGRAPH exceptions just as nv40 does :)
2008-05-02 01:36:30 +10:00
6d8062ac1e
nouveau: guard against channels potentially not having a context, fix nv50
2008-05-02 01:36:08 +10:00
77d20928b3
nouveau: disable all card interrupts when unknown PFIFO IRQ occurs.
...
This is possibly temporary. I can trigger an unending IRQ storm on G8x
in some circumstances, and have no idea how to handle that particular PFIFO
exception correctly yet.
2008-05-02 00:53:42 +10:00
5c4c778c0d
nouveau: restore original NV_PFIFO_CACHES_REASSIGN value in fifo handler
...
Doesn't fix any issue I've seen, but is a potential issue if a FIFO IRQ
occurs during channel creation/takedown.
2008-05-02 00:52:21 +10:00
bfbe4ade32
nouveau: gather nsource in trap_info()
...
The IRQ handling stuff really is a mess.. On the TODO :)
2008-05-02 00:51:00 +10:00
e317dfdabf
nv50: PGRAPH exception handling completely different from earlier chips
2008-05-02 00:06:22 +10:00
b92efd5956
nv50: I cave... Add nv84 initial context values.
...
I swore I'd actually do this properly and not go the horrible route
we did with nv4x, but I won't get around to it just yet with so many
*actually* interesting things to do first.. One day.
Since someone already added nv86, why not!
2008-05-01 23:50:44 +10:00
cb33133ef3
i915: fix off by one in VGA save/restore of AR & CR regs
...
Turns out it's important to save/restore AR14 in particular.
2008-04-29 12:39:38 -07:00
f31e04a960
nouveau: NV9x cards exist as well.
2008-04-29 19:34:22 +02:00
7f8e406085
Use fixed sized types in new ioctls
...
Make both crtc and the command argument 32 bits to avoid any 32-on-64 compat
issues.
2008-04-27 09:42:17 -07:00
b45fe49bcd
Enum-ectomy of vblank modesetting ioctl
...
Enum can be of pretty much any size since C leaves the choice of size up to the implementation. So avoid using it in new interfaces like the vblank pre- & post-modeset ioctl. Thanks to hch for spotting this.
2008-04-26 17:11:18 -07:00
feff72929e
i915: fix for compatibility mode
2008-04-23 17:17:16 +08:00
ce8c842518
i915: gfx hw and i945gme fixes from upstream
...
From Jesse and Zhenyu originally.
2008-04-22 16:08:17 +10:00
f0e38f5217
[I915] Handle tiled buffers in vblank tasklet
...
The vblank tasklet update code must build 2D blt commands with the
appropriate tiled flags.
2008-04-20 16:10:05 -07:00
21dbba5a22
On I965, use correct 3DSTATE_DRAWING_RECTANGLE command in vblank
...
The batchbuffer submission paths were fixed to use the 965-specific command,
but the vblank tasklet was not. When the older version is sent, the 965 will
lock up.
2008-04-20 01:56:02 -07:00
b986d7d2c9
Save and restore dsparb and d_state regs
2008-04-11 20:31:07 -07:00
1692d30cea
nv50: primitive i2c interrupt handler
2008-04-05 21:02:00 +02:00
3fc444a5e8
nv50: primitive display interrupt handler.
2008-04-03 01:13:31 +02:00
562f95ea96
nouveau: fix return from function..
...
dude kernel moduless use kernel errors :)
this fixes an oops on init when this codepath hits.
2008-03-31 11:34:48 +10:00
cf3c0123a0
nouveau: forgot to add a break
2008-03-30 14:50:41 +02:00
68b83a8813
nouveau: Add ctx values for nv86.
...
- Note that this may not work for all nv86.
2008-03-30 14:48:55 +02:00
753a4bdf1b
drm/r300: fix wait interface mixup
...
This interface was defined completely wrong, however userspace has only
ever used 4 values from it (0x1, 0x2, 0x3 and 0x6), so fix the interface to do what userspace actually expected but define new defines for new users to use
it properly.
2008-03-30 07:33:39 +10:00
1674d28179
r300: Correctly translate the value for the R300_CMD_WAIT command.
...
Previously, the R300_CMD_WAIT command would write the passed directly to the
hardware. However this is incorrect because the R300_WAIT_* values used are
internal interface values that do not map directly to the hardware.
The new function I have added translates the R300_WAIT_* values into appropriate
values for the hardware before writing the register.
Thanks to John Bridgman for pointing this out. :-)
2008-03-29 17:31:39 +00:00
a81d07f64d
nouveau: nv20 bios does not initialise PTIMER
...
The wait functions depend on PTIMER, so write the old (incorrect, but working) values for uninitialised hw
2008-03-25 18:32:26 +00:00
b0817a42e7
i915: fix oops on agp=off
...
Kernel bug 10289.
2008-03-24 18:52:26 +10:00
4323ee3e5b
Merge branch 'r500-fp'
2008-03-24 18:47:50 +10:00
24ba0c9c3b
nv40: voodoo - not quite.
2008-03-24 03:26:34 +11:00
6f4b3de284
nv40: allocate massive amount of PRAMIN for grctx on all chipsets.
...
More or less a workaround for issues on some chipsets where a context
switch results in critical data in PRAMIN being overwritten by the GPU.
The correct fix is known, but may take some time before it's a feasible
option.
2008-03-24 03:26:30 +11:00
36e11dd380
r500: fragment program upload is also used to upload constants.
...
Limit frag address to 8 bits
2008-03-21 16:59:52 +10:00
316979356f
drm: fixup r500fp submission
2008-03-20 14:20:53 +10:00
1021799b6c
nouveau: do not set on-board timer's numerator/denominator to bad values
2008-03-20 02:57:58 +00:00
9e4f908287
RADEON: switch over to new production microcode
...
This needs to be tested thoroughly before pushing to the
kernel.
2008-03-19 15:37:56 -04:00
d8af16d2a7
RADEON: production microcode for all radeons, r1xx-r6xx
...
This updated microcode is not in use yet.
2008-03-19 14:57:42 -04:00
a3c808d8fe
move some more r300 regs into not allowed on r500
2008-03-19 16:10:37 +10:00
d18c2c6842
drm: add new rs690 pci id
2008-03-18 09:07:45 +10:00
3add949403
initial r500 RS and FP register and upload code
2008-03-17 11:08:03 +10:00
1f96e9a982
drm/pcigart: fix the pci gart to use the drm_pci wrapper.
...
This is the correct fix for the RS690 and hopefully the dma coherent work.
For now we limit everybody to a 32-bit DMA mask but it is possible for
RS690 to use a 40-bit DMA mask for the GART table itself,
and the PCIE cards can use 40-bits for the table entries.
Signed-off-by: Dave Airlie <airlied@redhat.com>
2008-03-17 07:05:46 +10:00
1a2d8c4bfa
Avoid unnecessary waits for command regulator pause.
2008-03-16 20:07:14 +01:00
3a3a9485aa
[via] Remove some leftover vars.
2008-03-16 11:45:58 +01:00
7d3d15e67d
[via] The millionth fixup for the millionth-1 attempt to stabilize the AGP
...
DMA command submission. It's worth remembering that all new bright ideas on how
to make this command reader work properly and according to docs
will probably fail :( Bring in some old code.
2008-03-16 11:45:57 +01:00
563fe9dcd4
[via] Fix driver after vblank-rework merge.
2008-03-16 11:45:57 +01:00
5b1d9263d3
drm/rs690: set AGP_BASE_2 to 0
2008-03-16 14:00:16 +10:00
dd9eb923ed
drm: set rs690 gart base completly.
...
The docs state bits 4-11 represent bits 32-39 of a 40-bit address
2008-03-16 12:58:07 +10:00
9be916f353
Fix chip family for RV550
2008-03-12 11:16:12 -04:00
1766e1c07b
nv50: force channel vram access through vm
...
If we ever want to be able to use the 3D engine we have no choice. It
appears that the tiling setup (required for 3D on G8x) is in the page tables.
The immediate benefit of this change however is that it's now not possible
for a client to use the GPU to render over the top of important engine setup
tables, which also live in VRAM.
G8x VRAM size is limited to 512MiB at the moment, as we use a 1-1 mapping
of real vram pages to their offset within the start of a channel's VRAM
DMA object and only populate a single PDE for VRAM use.
2008-03-13 00:23:52 +11:00
88bd1e4a35
Merge branch 'intel-post-reloc'
...
Conflicts:
linux-core/drm_compat.c
linux-core/drm_compat.h
linux-core/drm_ttm.c
shared-core/i915_dma.c
Bump driver minor to 13 due to introduction of new
relocation type.
2008-03-12 11:34:29 +01:00
8a18d123f5
Avoid large kmallocs.
2008-03-12 09:49:27 +01:00
f13936f7fc
nouveau: move AGP reset to mem_init_agp
...
Also, power cycle PGRAPH when resetting AGP -- it seems to fix problems encountered by p0g on nv25
2008-03-11 16:45:35 +00:00
2848f04861
Switch from PIPE_VBLANK to PIPE_EVENT interrupts.
...
My 965GM gets interrupts stuck when using the old PIPE_VBLANK interrupt.
Switch to the PIPE_EVENT interrupt mechanism, and set the PIPE*STAT
registers to use START_VBLANK on 965 and VBLANK on previous chips.
2008-03-08 00:04:30 -08:00
ce3733572e
drm/radeon: check sarea_priv exists
2008-03-08 08:30:30 +10:00
1ccccbd4ce
nouveau: redo channel idle detection
...
Will hopefully work a bit better than previous code, which depended on
knowing the channel's most recent PUT value. Some chips always return
0 on reading these regs, and currently userspace is the only other entity
which knows the value.
2008-03-07 15:18:34 +11:00
cd924de029
nouveau: don't touch NV_USER regs on channel destroy.
...
Not only was this entirely pointless, it actually causes my NV30GL to
die randomly when channels are destroyed.
2008-03-07 15:18:34 +11:00
d5c0101252
ttm: make sure userspace can't destroy kernel create memory managers
...
this adds something to say the kernel initialised the memory region not
the userspace. and blocks userspace from deallocating kernel areas
2008-03-06 05:37:54 +10:00
180c9188f4
drm/ttm: add ioctl to get back memory managed area sized
...
taken from modesetting branch but could be useful outside it.
2008-03-06 05:31:50 +10:00
12574590cd
drm: reorganise minor number handling using code from modesetting branch
...
Rip out the whole head thing and replace it with an idr and drm_minor
structure.
2008-03-06 05:21:50 +10:00
638353103d
i915: Evict if relocatee buffer is CACHED_MAPPED before
...
writting relocations, otherwise the GPU probably sees some
inconsistent data. Fix fd.o bug#14656
2008-03-05 15:09:17 +08:00
a6a2f2c8c4
Clarify when WAIT_LAZY is relevant to users.
2008-03-04 13:45:41 -08:00
3332a0add6
Remove unused DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS.
2008-03-04 13:41:30 -08:00
63fd6f284d
[i915] 2D driver may reset Frame count value, this may lead driver
...
to leap it's vblank count a huge value.
This will stall some applications that switch video mode if vblank_mode is set to a non zero value in drirc.
2008-03-03 14:49:49 +08:00
612c22f131
Working revision.
2008-02-29 15:38:55 +01:00
2305100c0f
More post-ioctl work.
2008-02-29 13:25:55 +01:00
fd595fa4dc
Reinstate buffer idle before applying relocations.
2008-02-27 21:44:40 +01:00
72983ff301
Don't wait for buffer idle before applying relocations.
2008-02-27 19:46:28 +01:00
e87cec1968
[i915] Relocation fixes.
2008-02-26 10:47:05 +01:00
56bb29cf37
Make the execbuffer code reasonably safe against errors.
...
In particular -EAGAINs, which should be common during Xserver operation.
Also handle the fence creation failure case.
2008-02-26 00:05:26 +01:00
d6098db140
fix texture uploads with large 3d textures (bug 13980)
...
Texture uploads could hit the blitter coordinate limit, adjust the texture
offset when uploading the pieces. Make sure to check the end address of the
upload too.
2008-02-23 11:01:36 +01:00
0d32015974
nouveau: Remove some random (french) comment.
2008-02-22 19:28:54 +01:00
7e5f9c8bd3
nouveau: A single define of dma skips is more than enough.
2008-02-22 19:28:54 +01:00
b7086e6ae5
Fix one last occurance of struct _drm_i915_batchbuffer.
...
Thanks to Todd Merrill for pointing it out.
2008-02-22 11:22:52 -05:00
b0fee67a30
i915: Remove leading underscore from struct tags.
...
This matches the changes in mesa to use the system drm includes
for the definitions of the drm ioctl structs.
2008-02-22 00:12:39 -05:00
9d1061b8cf
fix SAREA
2008-02-20 22:23:31 +00:00
5d8c754bc2
[915]: more registers for S3 (DSPCLK_GATE_D, CACHE_MODE_0, MI_ARB_STATE)
...
Failing to preserve the MI_ARB_STATE register was causing FIFO underruns on
the VGA output on my HP 2510p after resume.
2008-02-16 20:14:49 -08:00
cd87e6352b
nouveau: no GART on ia64 either.
2008-02-16 03:50:29 +01:00
15cbde683f
nv40: actually init all tile regs.
2008-02-16 04:47:02 +11:00
373dbcf8b2
i915: Add a dri2 init path that gets the lock from the dri2 sarea.
2008-02-13 13:34:02 -05:00
db3f03ae35
i915: Only look up dev_priv->mmio_map if it's not already set up
2008-02-13 13:34:02 -05:00
ee15459483
i915: Add I915_PARAM_CHIPSET_ID param to get chipset ID.
2008-02-13 13:34:02 -05:00
4feb0638f1
i915: Make sarea_priv setup optional.
2008-02-13 13:34:02 -05:00
6f19473191
Fix saveGR array size
...
Make sure we have enough room for all the GR registers or we'll end up
clobbering the AR index register (which should actually be harmless
unless the BIOS is making an assumption about it).
2008-02-07 11:21:09 -08:00
8b6c96dedd
i915: save/restore interrupt state
...
On resume, if the interrupt state isn't restored correctly, we may end
up with a flood of unexpected or ill-timed interrupts, which could cause
the kernel to disable the interrupt or vblank events to happen at the
wrong time. So save/restore them properly.
2008-02-07 10:48:08 -08:00
76748efae2
i915: Re-report breadcrumbs on poll to the fence manager,
...
since a breadcrumb may actually turn up before a corresponding fence object
has been placed on the fence ring.
2008-02-05 10:36:49 +01:00
a0781e7622
nouveau: make nv34 work every time, not just every 2nd time
...
And make nv30_graph_init a bit more like mmio-traces
2008-02-04 16:38:31 +00:00
733e07663e
nouveau: NV40 can/should now be able to run after the blob.
...
- Moved the fix from the ddx to drm, because it seemed more appropriate.
- Don't be shy, report if it works for you or not.
2008-02-02 12:46:47 +01:00
47ee6237fe
i915: Avoid calling drm_fence_flush_old excessively.
2008-01-30 22:14:02 +01:00
Dave Airlie
Alex Deucher
Ben Skeggs
Jesse Barnes
Maarten Maathuis
Jesse Barnes
Jesse Barnes
Xiang, Haihao
Dave Airlie
Keith Packard
Oliver McFadden
Stuart Bennett
Alex Deucher
Thomas Hellstrom
Alex Deucher
Eric Anholt
Zou Nan hai
Roland Scheidegger
Kristian Høgsberg
Alan Hourihane
Stephane Marchesin
Jesse Barnes